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authorPeter Maydell <peter.maydell@linaro.org>2017-01-09 14:04:20 +0000
committerPeter Maydell <peter.maydell@linaro.org>2017-01-09 14:04:20 +0000
commitd5510fa80cf4629fa4a7c0adbdff311ed6e76148 (patch)
tree139f14ced4eb89ebbcb957fd29369f3028e13e39
parent8305f9bdf7ca41ee5cabe018fb37b73472c1162d (diff)
downloadqemu-arm-d5510fa80cf4629fa4a7c0adbdff311ed6e76148.tar.gz
hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ
Augment the GICv3's QOM device interface by adding two new sets of sysbus IRQ lines, to signal VIRQ and VFIQ to each CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/intc/arm_gicv3_common.c6
-rw-r--r--include/hw/intc/arm_gicv3_common.h2
2 files changed, 8 insertions, 0 deletions
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 0aa9b9ca66..0ee67a40b5 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -126,6 +126,12 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
for (i = 0; i < s->num_cpu; i++) {
sysbus_init_irq(sbd, &s->cpu[i].parent_fiq);
}
+ for (i = 0; i < s->num_cpu; i++) {
+ sysbus_init_irq(sbd, &s->cpu[i].parent_virq);
+ }
+ for (i = 0; i < s->num_cpu; i++) {
+ sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq);
+ }
memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
"gicv3_dist", 0x10000);
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
index 341a3118f0..beb2c7763e 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -145,6 +145,8 @@ struct GICv3CPUState {
CPUState *cpu;
qemu_irq parent_irq;
qemu_irq parent_fiq;
+ qemu_irq parent_virq;
+ qemu_irq parent_vfiq;
/* Redistributor */
uint32_t level; /* Current IRQ level */