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authorPeter Maydell <peter.maydell@linaro.org>2017-01-09 14:04:20 +0000
committerPeter Maydell <peter.maydell@linaro.org>2017-01-09 14:04:20 +0000
commitae889cfda263370a3c407f6974a916e5ddc8608e (patch)
tree61df627043c94dafd680fcbb26e874eabcde69ce
parent80c2dc7f298f45ffdaffd433fdce31f60c1f9ce4 (diff)
downloadqemu-arm-ae889cfda263370a3c407f6974a916e5ddc8608e.tar.gz
target-arm: Expose output GPIO line for VCPU maintenance interrupt
The GICv3 support for virtualization includes an outbound maintenance interrupt signal which is asserted when the CPU interface wants to signal to the hypervisor that it needs attention. Expose this as an outbound GPIO line from the CPU object which can be wired up as a physical interrupt line by the board code (as we do already for the CPU timers). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-rw-r--r--target/arm/cpu.c3
-rw-r--r--target/arm/cpu.h2
2 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f5cb30af6c..893208677e 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -466,6 +466,9 @@ static void arm_cpu_initfn(Object *obj)
arm_gt_stimer_cb, cpu);
qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
ARRAY_SIZE(cpu->gt_timer_outputs));
+
+ qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
+ "gicv3-maintenance-interrupt", 1);
#endif
/* DTB consumers generally don't in fact care what the 'compatible'
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ab119e62ab..764b511c5b 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -555,6 +555,8 @@ struct ARMCPU {
QEMUTimer *gt_timer[NUM_GTIMERS];
/* GPIO outputs for generic timer */
qemu_irq gt_timer_outputs[NUM_GTIMERS];
+ /* GPIO output for GICv3 maintenance interrupt signal */
+ qemu_irq gicv3_maintenance_interrupt;
/* MemoryRegion to use for secure physical accesses */
MemoryRegion *secure_memory;