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authorPeter Maydell <peter.maydell@linaro.org>2016-06-09 16:02:37 +0100
committerPeter Maydell <peter.maydell@linaro.org>2016-06-09 16:13:58 +0100
commit48670bed94f9b681833a93521b239f3c79ef10fa (patch)
tree0b553f56c92d7364519ec21713148fa2141aa4f6
parenta6d86d7d6bbbee2479b3091c694a70b77770ad24 (diff)
target-arm: Define new arm_is_el3_or_mon() function
The GICv3 system registers need to know if the CPU is AArch64 in EL3 or AArch32 in Monitor mode. This happens to be the first part of the check for arm_is_secure(), so factor it out into a new arm_is_el3_or_mon() function that the GIC can also use. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
-rw-r--r--target-arm/cpu.h13
1 files changed, 11 insertions, 2 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 17d80510da..2c2b8f7b52 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1144,8 +1144,8 @@ static inline bool arm_is_secure_below_el3(CPUARMState *env)
}
}
-/* Return true if the processor is in secure state */
-static inline bool arm_is_secure(CPUARMState *env)
+/* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
+static inline bool arm_is_el3_or_mon(CPUARMState *env)
{
if (arm_feature(env, ARM_FEATURE_EL3)) {
if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
@@ -1157,6 +1157,15 @@ static inline bool arm_is_secure(CPUARMState *env)
return true;
}
}
+ return false;
+}
+
+/* Return true if the processor is in secure state */
+static inline bool arm_is_secure(CPUARMState *env)
+{
+ if (arm_is_el3_or_mon(env)) {
+ return true;
+ }
return arm_is_secure_below_el3(env);
}