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authorRichard Henderson <richard.henderson@linaro.org>2022-05-05 11:30:33 -0500
committerRichard Henderson <richard.henderson@linaro.org>2022-05-05 11:30:33 -0500
commite91b8994115d2f093e7556c9af2d051a26a98cfb (patch)
treebed4014f41aaa2fb734d59e20197cdc217ad32b9
parent5d5104260222cd7ffaaeb555727808f479e7103b (diff)
parent99a50d1a67c602126fc2b3a4812d3000eba9bf34 (diff)
Merge tag 'pull-target-arm-20220505' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * Enable read access to performance counters from EL0 * Enable SCTLR_EL1.BT0 for aarch64-linux-user * Refactoring of cpreg handling # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmJzlJYZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3rQXEACqtWhESD9ZJ0T1DfiWh7HX # KXZuvB5C4kEdY8KXPJsdFM47KGMB29AI1pfqN5oRvalGG40ROM1HNTO44LSjKgUr # b+aEq0bcbOJQuhfc5EPoh3b9wekowxlBYsH3Zq251J6ua6dRd1iqdeGXFIZbn02x # RY5lXB2wgWh8LnF+qwoLiIrqJWsJ8PSOolyl0LrKjI3Z22UboK1Y5K0sbJBlavX4 # xKEyd4Af1Jq+1GcleSymAjcNF1iO+38w6rrFSgMWj+f3HSjKCk+MHU78rfqVNa88 # ESRjBj1x3c8kRzNzy+Q8ntJ5QzREvFDpUYBC9lvnoLKQ6xRJWDvvZQw2YJGsH8sB # Xgg8fQ75iYEQdN4SHLWn24OwZpKuzTZ4QYm0d02GiAZCGXgAFEIKG62lBd3UJTAy # 6wTUdjuLv/KA+Lc3qdvmFfOVxfPh728VvFl55IoGXZv9FFrxvrluLEgr3TIje9W3 # 0r1FcjtAuuTHzKiaf8UsmvMW9nR550L1xQ+uMY8GKQvQgSvkf050srVZS05GFItH # DqCUv++hsyi0b44J377cUKkAEOdH/rhV20pvvfoJthRgmHLNN5LG61JI9eK9JXzl # +AYpbxAC3R6f0dp6/31D0ZRhW7wcC/rt1EVK/iACVKoGo8hZf3lC64y2+3TVoApF # DdCadVNnR9eUFWh1inGXKQ== # =Q7ra # -----END PGP SIGNATURE----- # gpg: Signature made Thu 05 May 2022 04:10:46 AM CDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] * tag 'pull-target-arm-20220505' of https://git.linaro.org/people/pmaydell/qemu-arm: (23 commits) target/arm: read access to performance counters from EL0 target/arm: Add isar_feature_{aa64,any}_ras target/arm: Add isar predicates for FEAT_Debugv8p2 target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable target/arm: Reformat comments in add_cpreg_to_hashtable target/arm: Perform override check early in add_cpreg_to_hashtable target/arm: Hoist isbanked computation in add_cpreg_to_hashtable target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable target/arm: Hoist computation of key in add_cpreg_to_hashtable target/arm: Merge allocation of the cpreg and its name target/arm: Store cpregs key in the hash table directly target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases target/arm: Name CPSecureState type target/arm: Name CPState type target/arm: Change cpreg access permissions to enum target/arm: Avoid bare abort() or assert(0) target/arm: Reorg ARMCPRegInfo type field bits target/arm: Make some more cpreg data static const target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat
-rw-r--r--hw/arm/pxa2xx.c2
-rw-r--r--hw/arm/pxa2xx_pic.c2
-rw-r--r--hw/intc/arm_gicv3_cpuif.c6
-rw-r--r--hw/intc/arm_gicv3_kvm.c3
-rw-r--r--target/arm/cpregs.h453
-rw-r--r--target/arm/cpu.c25
-rw-r--r--target/arm/cpu.h393
-rw-r--r--target/arm/cpu64.c2
-rw-r--r--target/arm/cpu_tcg.c5
-rw-r--r--target/arm/gdbstub.c5
-rw-r--r--target/arm/helper.c356
-rw-r--r--target/arm/hvf/hvf.c2
-rw-r--r--target/arm/kvm-stub.c4
-rw-r--r--target/arm/kvm.c4
-rw-r--r--target/arm/machine.c4
-rw-r--r--target/arm/op_helper.c53
-rw-r--r--target/arm/translate-a64.c14
-rw-r--r--target/arm/translate-neon.c2
-rw-r--r--target/arm/translate.c13
-rw-r--r--tests/tcg/aarch64/Makefile.target6
-rw-r--r--tests/tcg/aarch64/bti-3.c42
21 files changed, 735 insertions, 661 deletions
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index a6f938f115..f4f687df68 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -30,6 +30,7 @@
#include "qemu/cutils.h"
#include "qemu/log.h"
#include "qom/object.h"
+#include "target/arm/cpregs.h"
static struct {
hwaddr io_base;
@@ -383,7 +384,6 @@ static const ARMCPRegInfo pxa_cp_reginfo[] = {
{ .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_IO,
.readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
- REGINFO_SENTINEL
};
static void pxa2xx_setup_cp14(PXA2xxState *s)
diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
index ed032fed54..47132ab982 100644
--- a/hw/arm/pxa2xx_pic.c
+++ b/hw/arm/pxa2xx_pic.c
@@ -17,6 +17,7 @@
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "qom/object.h"
+#include "target/arm/cpregs.h"
#define ICIP 0x00 /* Interrupt Controller IRQ Pending register */
#define ICMR 0x04 /* Interrupt Controller Mask register */
@@ -256,7 +257,6 @@ static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
REGINFO_FOR_PIC_CP("ICLR2", 8),
REGINFO_FOR_PIC_CP("ICFP2", 9),
REGINFO_FOR_PIC_CP("ICPR2", 0xa),
- REGINFO_SENTINEL
};
static const MemoryRegionOps pxa2xx_pic_ops = {
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 8404f46ee0..9efba798f8 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -20,6 +20,7 @@
#include "gicv3_internal.h"
#include "hw/irq.h"
#include "cpu.h"
+#include "target/arm/cpregs.h"
/*
* Special case return value from hppvi_index(); must be larger than
@@ -2427,7 +2428,6 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
.readfn = icc_igrpen1_el3_read,
.writefn = icc_igrpen1_el3_write,
},
- REGINFO_SENTINEL
};
static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -2681,7 +2681,6 @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = {
.readfn = ich_vmcr_read,
.writefn = ich_vmcr_write,
},
- REGINFO_SENTINEL
};
static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = {
@@ -2699,7 +2698,6 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] = {
.readfn = ich_ap_read,
.writefn = ich_ap_write,
},
- REGINFO_SENTINEL
};
static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = {
@@ -2731,7 +2729,6 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] = {
.readfn = ich_ap_read,
.writefn = ich_ap_write,
},
- REGINFO_SENTINEL
};
static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, void *opaque)
@@ -2806,7 +2803,6 @@ void gicv3_init_cpuif(GICv3State *s)
.readfn = ich_lr_read,
.writefn = ich_lr_write,
},
- REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, lr_regset);
}
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index 06f5aceee5..2922c516e5 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -31,6 +31,8 @@
#include "vgic_common.h"
#include "migration/blocker.h"
#include "qom/object.h"
+#include "target/arm/cpregs.h"
+
#ifdef DEBUG_GICV3_KVM
#define DPRINTF(fmt, ...) \
@@ -733,7 +735,6 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
*/
.resetfn = arm_gicv3_icc_reset,
},
- REGINFO_SENTINEL
};
/**
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
new file mode 100644
index 0000000000..73984549d2
--- /dev/null
+++ b/target/arm/cpregs.h
@@ -0,0 +1,453 @@
+/*
+ * QEMU ARM CP Register access and descriptions
+ *
+ * Copyright (c) 2022 Linaro Ltd
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+
+#ifndef TARGET_ARM_CPREGS_H
+#define TARGET_ARM_CPREGS_H
+
+/*
+ * ARMCPRegInfo type field bits:
+ */
+enum {
+ /*
+ * Register must be handled specially during translation.
+ * The method is one of the values below:
+ */
+ ARM_CP_SPECIAL_MASK = 0x000f,
+ /* Special: no change to PE state: writes ignored, reads ignored. */
+ ARM_CP_NOP = 0x0001,
+ /* Special: sysreg is WFI, for v5 and v6. */
+ ARM_CP_WFI = 0x0002,
+ /* Special: sysreg is NZCV. */
+ ARM_CP_NZCV = 0x0003,
+ /* Special: sysreg is CURRENTEL. */
+ ARM_CP_CURRENTEL = 0x0004,
+ /* Special: sysreg is DC ZVA or similar. */
+ ARM_CP_DC_ZVA = 0x0005,
+ ARM_CP_DC_GVA = 0x0006,
+ ARM_CP_DC_GZVA = 0x0007,
+
+ /* Flag: reads produce resetvalue; writes ignored. */
+ ARM_CP_CONST = 1 << 4,
+ /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */
+ ARM_CP_64BIT = 1 << 5,
+ /*
+ * Flag: TB should not be ended after a write to this register
+ * (the default is that the TB ends after cp writes).
+ */
+ ARM_CP_SUPPRESS_TB_END = 1 << 6,
+ /*
+ * Flag: Permit a register definition to override a previous definition
+ * for the same (cp, is64, crn, crm, opc1, opc2) tuple: either the new
+ * or the old must have the ARM_CP_OVERRIDE bit set.
+ */
+ ARM_CP_OVERRIDE = 1 << 7,
+ /*
+ * Flag: Register is an alias view of some underlying state which is also
+ * visible via another register, and that the other register is handling
+ * migration and reset; registers marked ARM_CP_ALIAS will not be migrated
+ * but may have their state set by syncing of register state from KVM.
+ */
+ ARM_CP_ALIAS = 1 << 8,
+ /*
+ * Flag: Register does I/O and therefore its accesses need to be marked
+ * with gen_io_start() and also end the TB. In particular, registers which
+ * implement clocks or timers require this.
+ */
+ ARM_CP_IO = 1 << 9,
+ /*
+ * Flag: Register has no underlying state and does not support raw access
+ * for state saving/loading; it will not be used for either migration or
+ * KVM state synchronization. Typically this is for "registers" which are
+ * actually used as instructions for cache maintenance and so on.
+ */
+ ARM_CP_NO_RAW = 1 << 10,
+ /*
+ * Flag: The read or write hook might raise an exception; the generated
+ * code will synchronize the CPU state before calling the hook so that it
+ * is safe for the hook to call raise_exception().
+ */
+ ARM_CP_RAISES_EXC = 1 << 11,
+ /*
+ * Flag: Writes to the sysreg might change the exception level - typically
+ * on older ARM chips. For those cases we need to re-read the new el when
+ * recomputing the translation flags.
+ */
+ ARM_CP_NEWEL = 1 << 12,
+ /*
+ * Flag: Access check for this sysreg is identical to accessing FPU state
+ * from an instruction: use translation fp_access_check().
+ */
+ ARM_CP_FPU = 1 << 13,
+ /*
+ * Flag: Access check for this sysreg is identical to accessing SVE state
+ * from an instruction: use translation sve_access_check().
+ */
+ ARM_CP_SVE = 1 << 14,
+ /* Flag: Do not expose in gdb sysreg xml. */
+ ARM_CP_NO_GDB = 1 << 15,
+};
+
+/*
+ * Valid values for ARMCPRegInfo state field, indicating which of
+ * the AArch32 and AArch64 execution states this register is visible in.
+ * If the reginfo doesn't explicitly specify then it is AArch32 only.
+ * If the reginfo is declared to be visible in both states then a second
+ * reginfo is synthesised for the AArch32 view of the AArch64 register,
+ * such that the AArch32 view is the lower 32 bits of the AArch64 one.
+ * Note that we rely on the values of these enums as we iterate through
+ * the various states in some places.
+ */
+typedef enum {
+ ARM_CP_STATE_AA32 = 0,
+ ARM_CP_STATE_AA64 = 1,
+ ARM_CP_STATE_BOTH = 2,
+} CPState;
+
+/*
+ * ARM CP register secure state flags. These flags identify security state
+ * attributes for a given CP register entry.
+ * The existence of both or neither secure and non-secure flags indicates that
+ * the register has both a secure and non-secure hash entry. A single one of
+ * these flags causes the register to only be hashed for the specified
+ * security state.
+ * Although definitions may have any combination of the S/NS bits, each
+ * registered entry will only have one to identify whether the entry is secure
+ * or non-secure.
+ */
+typedef enum {
+ ARM_CP_SECSTATE_BOTH = 0, /* define one cpreg for each secstate */
+ ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */
+ ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */
+} CPSecureState;
+
+/*
+ * Access rights:
+ * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
+ * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
+ * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
+ * (ie any of the privileged modes in Secure state, or Monitor mode).
+ * If a register is accessible in one privilege level it's always accessible
+ * in higher privilege levels too. Since "Secure PL1" also follows this rule
+ * (ie anything visible in PL2 is visible in S-PL1, some things are only
+ * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
+ * terminology a little and call this PL3.
+ * In AArch64 things are somewhat simpler as the PLx bits line up exactly
+ * with the ELx exception levels.
+ *
+ * If access permissions for a register are more complex than can be
+ * described with these bits, then use a laxer set of restrictions, and
+ * do the more restrictive/complex check inside a helper function.
+ */
+typedef enum {
+ PL3_R = 0x80,
+ PL3_W = 0x40,
+ PL2_R = 0x20 | PL3_R,
+ PL2_W = 0x10 | PL3_W,
+ PL1_R = 0x08 | PL2_R,
+ PL1_W = 0x04 | PL2_W,
+ PL0_R = 0x02 | PL1_R,
+ PL0_W = 0x01 | PL1_W,
+
+ /*
+ * For user-mode some registers are accessible to EL0 via a kernel
+ * trap-and-emulate ABI. In this case we define the read permissions
+ * as actually being PL0_R. However some bits of any given register
+ * may still be masked.
+ */
+#ifdef CONFIG_USER_ONLY
+ PL0U_R = PL0_R,
+#else
+ PL0U_R = PL1_R,
+#endif
+
+ PL3_RW = PL3_R | PL3_W,
+ PL2_RW = PL2_R | PL2_W,
+ PL1_RW = PL1_R | PL1_W,
+ PL0_RW = PL0_R | PL0_W,
+} CPAccessRights;
+
+typedef enum CPAccessResult {
+ /* Access is permitted */
+ CP_ACCESS_OK = 0,
+
+ /*
+ * Combined with one of the following, the low 2 bits indicate the
+ * target exception level. If 0, the exception is taken to the usual
+ * target EL (EL1 or PL1 if in EL0, otherwise to the current EL).
+ */
+ CP_ACCESS_EL_MASK = 3,
+
+ /*
+ * Access fails due to a configurable trap or enable which would
+ * result in a categorized exception syndrome giving information about
+ * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
+ * 0xc or 0x18).
+ */
+ CP_ACCESS_TRAP = (1 << 2),
+ CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP | 2,
+ CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP | 3,
+
+ /*
+ * Access fails and results in an exception syndrome 0x0 ("uncategorized").
+ * Note that this is not a catch-all case -- the set of cases which may
+ * result in this failure is specifically defined by the architecture.
+ */
+ CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
+ CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = CP_ACCESS_TRAP_UNCATEGORIZED | 2,
+ CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = CP_ACCESS_TRAP_UNCATEGORIZED | 3,
+} CPAccessResult;
+
+typedef struct ARMCPRegInfo ARMCPRegInfo;
+
+/*
+ * Access functions for coprocessor registers. These cannot fail and
+ * may not raise exceptions.
+ */
+typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
+typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
+ uint64_t value);
+/* Access permission check functions for coprocessor registers. */
+typedef CPAccessResult CPAccessFn(CPUARMState *env,
+ const ARMCPRegInfo *opaque,
+ bool isread);
+/* Hook function for register reset */
+typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
+
+#define CP_ANY 0xff
+
+/* Definition of an ARM coprocessor register */
+struct ARMCPRegInfo {
+ /* Name of register (useful mainly for debugging, need not be unique) */
+ const char *name;
+ /*
+ * Location of register: coprocessor number and (crn,crm,opc1,opc2)
+ * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
+ * 'wildcard' field -- any value of that field in the MRC/MCR insn
+ * will be decoded to this register. The register read and write
+ * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
+ * used by the program, so it is possible to register a wildcard and
+ * then behave differently on read/write if necessary.
+ * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
+ * must both be zero.
+ * For AArch64-visible registers, opc0 is also used.
+ * Since there are no "coprocessors" in AArch64, cp is purely used as a
+ * way to distinguish (for KVM's benefit) guest-visible system registers
+ * from demuxed ones provided to preserve the "no side effects on
+ * KVM register read/write from QEMU" semantics. cp==0x13 is guest
+ * visible (to match KVM's encoding); cp==0 will be converted to
+ * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
+ */
+ uint8_t cp;
+ uint8_t crn;
+ uint8_t crm;
+ uint8_t opc0;
+ uint8_t opc1;
+ uint8_t opc2;
+ /* Execution state in which this register is visible: ARM_CP_STATE_* */
+ CPState state;
+ /* Register type: ARM_CP_* bits/values */
+ int type;
+ /* Access rights: PL*_[RW] */
+ CPAccessRights access;
+ /* Security state: ARM_CP_SECSTATE_* bits/values */
+ CPSecureState secure;
+ /*
+ * The opaque pointer passed to define_arm_cp_regs_with_opaque() when
+ * this register was defined: can be used to hand data through to the
+ * register read/write functions, since they are passed the ARMCPRegInfo*.
+ */
+ void *opaque;
+ /*
+ * Value of this register, if it is ARM_CP_CONST. Otherwise, if
+ * fieldoffset is non-zero, the reset value of the register.
+ */
+ uint64_t resetvalue;
+ /*
+ * Offset of the field in CPUARMState for this register.
+ * This is not needed if either:
+ * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
+ * 2. both readfn and writefn are specified
+ */
+ ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
+
+ /*
+ * Offsets of the secure and non-secure fields in CPUARMState for the
+ * register if it is banked. These fields are only used during the static
+ * registration of a register. During hashing the bank associated
+ * with a given security state is copied to fieldoffset which is used from
+ * there on out.
+ *
+ * It is expected that register definitions use either fieldoffset or
+ * bank_fieldoffsets in the definition but not both. It is also expected
+ * that both bank offsets are set when defining a banked register. This
+ * use indicates that a register is banked.
+ */
+ ptrdiff_t bank_fieldoffsets[2];
+
+ /*
+ * Function for making any access checks for this register in addition to
+ * those specified by the 'access' permissions bits. If NULL, no extra
+ * checks required. The access check is performed at runtime, not at
+ * translate time.
+ */
+ CPAccessFn *accessfn;
+ /*
+ * Function for handling reads of this register. If NULL, then reads
+ * will be done by loading from the offset into CPUARMState specified
+ * by fieldoffset.
+ */
+ CPReadFn *readfn;
+ /*
+ * Function for handling writes of this register. If NULL, then writes
+ * will be done by writing to the offset into CPUARMState specified
+ * by fieldoffset.
+ */
+ CPWriteFn *writefn;
+ /*
+ * Function for doing a "raw" read; used when we need to copy
+ * coprocessor state to the kernel for KVM or out for
+ * migration. This only needs to be provided if there is also a
+ * readfn and it has side effects (for instance clear-on-read bits).
+ */
+ CPReadFn *raw_readfn;
+ /*
+ * Function for doing a "raw" write; used when we need to copy KVM
+ * kernel coprocessor state into userspace, or for inbound
+ * migration. This only needs to be provided if there is also a
+ * writefn and it masks out "unwritable" bits or has write-one-to-clear
+ * or similar behaviour.
+ */
+ CPWriteFn *raw_writefn;
+ /*
+ * Function for resetting the register. If NULL, then reset will be done
+ * by writing resetvalue to the field specified in fieldoffset. If
+ * fieldoffset is 0 then no reset will be done.
+ */
+ CPResetFn *resetfn;
+
+ /*
+ * "Original" writefn and readfn.
+ * For ARMv8.1-VHE register aliases, we overwrite the read/write
+ * accessor functions of various EL1/EL0 to perform the runtime
+ * check for which sysreg should actually be modified, and then
+ * forwards the operation. Before overwriting the accessors,
+ * the original function is copied here, so that accesses that
+ * really do go to the EL1/EL0 version proceed normally.
+ * (The corresponding EL2 register is linked via opaque.)
+ */
+ CPReadFn *orig_readfn;
+ CPWriteFn *orig_writefn;
+};
+
+/*
+ * Macros which are lvalues for the field in CPUARMState for the
+ * ARMCPRegInfo *ri.
+ */
+#define CPREG_FIELD32(env, ri) \
+ (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
+#define CPREG_FIELD64(env, ri) \
+ (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
+
+void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *reg,
+ void *opaque);
+
+static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
+{
+ define_one_arm_cp_reg_with_opaque(cpu, regs, NULL);
+}
+
+void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs,
+ void *opaque, size_t len);
+
+#define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE) \
+ do { \
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \
+ define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE, \
+ ARRAY_SIZE(REGS)); \
+ } while (0)
+
+#define define_arm_cp_regs(CPU, REGS) \
+ define_arm_cp_regs_with_opaque(CPU, REGS, NULL)
+
+const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
+
+/*
+ * Definition of an ARM co-processor register as viewed from
+ * userspace. This is used for presenting sanitised versions of
+ * registers to userspace when emulating the Linux AArch64 CPU
+ * ID/feature ABI (advertised as HWCAP_CPUID).
+ */
+typedef struct ARMCPRegUserSpaceInfo {
+ /* Name of register */
+ const char *name;
+
+ /* Is the name actually a glob pattern */
+ bool is_glob;
+
+ /* Only some bits are exported to user space */
+ uint64_t exported_bits;
+
+ /* Fixed bits are applied after the mask */
+ uint64_t fixed_bits;
+} ARMCPRegUserSpaceInfo;
+
+void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
+ const ARMCPRegUserSpaceInfo *mods,
+ size_t mods_len);
+
+#define modify_arm_cp_regs(REGS, MODS) \
+ do { \
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(MODS) == 0); \
+ modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS), \
+ MODS, ARRAY_SIZE(MODS)); \
+ } while (0)
+
+/* CPWriteFn that can be used to implement writes-ignored behaviour */
+void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value);
+/* CPReadFn that can be used for read-as-zero behaviour */
+uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
+
+/*
+ * CPResetFn that does nothing, for use if no reset is required even
+ * if fieldoffset is non zero.
+ */
+void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
+
+/*
+ * Return true if this reginfo struct's field in the cpu state struct
+ * is 64 bits wide.
+ */
+static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
+{
+ return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
+}
+
+static inline bool cp_access_ok(int current_el,
+ const ARMCPRegInfo *ri, int isread)
+{
+ return (ri->access >> ((current_el * 2) + isread)) & 1;
+}
+
+/* Raw read of a coprocessor register (as needed for migration, etc) */
+uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
+
+#endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index e46a766d77..01176b2569 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -43,6 +43,7 @@
#include "kvm_arm.h"
#include "disas/capstone.h"
#include "fpu/softfloat.h"
+#include "cpregs.h"
static void arm_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -116,7 +117,7 @@ static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
ARMCPRegInfo *ri = value;
ARMCPU *cpu = opaque;
- if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
+ if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) {
return;
}
@@ -152,7 +153,7 @@ static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
ARMCPU *cpu = opaque;
uint64_t oldvalue, newvalue;
- if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
+ if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
return;
}
@@ -197,6 +198,8 @@ static void arm_cpu_reset(DeviceState *dev)
/* Enable all PAC keys. */
env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
SCTLR_EnDA | SCTLR_EnDB);
+ /* Trap on btype=3 for PACIxSP. */
+ env->cp15.sctlr_el[1] |= SCTLR_BT0;
/* and to the FP/Neon instructions */
env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
/* and to the SVE instructions */
@@ -1068,27 +1071,13 @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
}
-static void cpreg_hashtable_data_destroy(gpointer data)
-{
- /*
- * Destroy function for cpu->cp_regs hashtable data entries.
- * We must free the name string because it was g_strdup()ed in
- * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
- * from r->name because we know we definitely allocated it.
- */
- ARMCPRegInfo *r = data;
-
- g_free((void *)r->name);
- g_free(r);
-}
-
static void arm_cpu_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu_set_cpustate_pointers(cpu);
- cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
- g_free, cpreg_hashtable_data_destroy);
+ cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
+ NULL, g_free);
QLIST_INIT(&cpu->pre_el_change_hooks);
QLIST_INIT(&cpu->el_change_hooks);
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index db8ff04449..ca01f909a8 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2595,144 +2595,6 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
return kvmid;
}
-/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
- * special-behaviour cp reg and bits [11..8] indicate what behaviour
- * it has. Otherwise it is a simple cp reg, where CONST indicates that
- * TCG can assume the value to be constant (ie load at translate time)
- * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
- * indicates that the TB should not be ended after a write to this register
- * (the default is that the TB ends after cp writes). OVERRIDE permits
- * a register definition to override a previous definition for the
- * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
- * old must have the OVERRIDE bit set.
- * ALIAS indicates that this register is an alias view of some underlying
- * state which is also visible via another register, and that the other
- * register is handling migration and reset; registers marked ALIAS will not be
- * migrated but may have their state set by syncing of register state from KVM.
- * NO_RAW indicates that this register has no underlying state and does not
- * support raw access for state saving/loading; it will not be used for either
- * migration or KVM state synchronization. (Typically this is for "registers"
- * which are actually used as instructions for cache maintenance and so on.)
- * IO indicates that this register does I/O and therefore its accesses
- * need to be marked with gen_io_start() and also end the TB. In particular,
- * registers which implement clocks or timers require this.
- * RAISES_EXC is for when the read or write hook might raise an exception;
- * the generated code will synchronize the CPU state before calling the hook
- * so that it is safe for the hook to call raise_exception().
- * NEWEL is for writes to registers that might change the exception
- * level - typically on older ARM chips. For those cases we need to
- * re-read the new el when recomputing the translation flags.
- */
-#define ARM_CP_SPECIAL 0x0001
-#define ARM_CP_CONST 0x0002
-#define ARM_CP_64BIT 0x0004
-#define ARM_CP_SUPPRESS_TB_END 0x0008
-#define ARM_CP_OVERRIDE 0x0010
-#define ARM_CP_ALIAS 0x0020
-#define ARM_CP_IO 0x0040
-#define ARM_CP_NO_RAW 0x0080
-#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100)
-#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200)
-#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
-#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400)
-#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
-#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600)
-#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700)
-#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA
-#define ARM_CP_FPU 0x1000
-#define ARM_CP_SVE 0x2000
-#define ARM_CP_NO_GDB 0x4000
-#define ARM_CP_RAISES_EXC 0x8000
-#define ARM_CP_NEWEL 0x10000
-/* Used only as a terminator for ARMCPRegInfo lists */
-#define ARM_CP_SENTINEL 0xfffff
-/* Mask of only the flag bits in a type field */
-#define ARM_CP_FLAG_MASK 0x1f0ff
-
-/* Valid values for ARMCPRegInfo state field, indicating which of
- * the AArch32 and AArch64 execution states this register is visible in.
- * If the reginfo doesn't explicitly specify then it is AArch32 only.
- * If the reginfo is declared to be visible in both states then a second
- * reginfo is synthesised for the AArch32 view of the AArch64 register,
- * such that the AArch32 view is the lower 32 bits of the AArch64 one.
- * Note that we rely on the values of these enums as we iterate through
- * the various states in some places.
- */
-enum {
- ARM_CP_STATE_AA32 = 0,
- ARM_CP_STATE_AA64 = 1,
- ARM_CP_STATE_BOTH = 2,
-};
-
-/* ARM CP register secure state flags. These flags identify security state
- * attributes for a given CP register entry.
- * The existence of both or neither secure and non-secure flags indicates that
- * the register has both a secure and non-secure hash entry. A single one of
- * these flags causes the register to only be hashed for the specified
- * security state.
- * Although definitions may have any combination of the S/NS bits, each
- * registered entry will only have one to identify whether the entry is secure
- * or non-secure.
- */
-enum {
- ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */
- ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */
-};
-
-/* Return true if cptype is a valid type field. This is used to try to
- * catch errors where the sentinel has been accidentally left off the end
- * of a list of registers.
- */
-static inline bool cptype_valid(int cptype)
-{
- return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
- || ((cptype & ARM_CP_SPECIAL) &&
- ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
-}
-
-/* Access rights:
- * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
- * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
- * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
- * (ie any of the privileged modes in Secure state, or Monitor mode).
- * If a register is accessible in one privilege level it's always accessible
- * in higher privilege levels too. Since "Secure PL1" also follows this rule
- * (ie anything visible in PL2 is visible in S-PL1, some things are only
- * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
- * terminology a little and call this PL3.
- * In AArch64 things are somewhat simpler as the PLx bits line up exactly
- * with the ELx exception levels.
- *
- * If access permissions for a register are more complex than can be
- * described with these bits, then use a laxer set of restrictions, and
- * do the more restrictive/complex check inside a helper function.
- */
-#define PL3_R 0x80
-#define PL3_W 0x40
-#define PL2_R (0x20 | PL3_R)
-#define PL2_W (0x10 | PL3_W)
-#define PL1_R (0x08 | PL2_R)
-#define PL1_W (0x04 | PL2_W)
-#define PL0_R (0x02 | PL1_R)
-#define PL0_W (0x01 | PL1_W)
-
-/*
- * For user-mode some registers are accessible to EL0 via a kernel
- * trap-and-emulate ABI. In this case we define the read permissions
- * as actually being PL0_R. However some bits of any given register
- * may still be masked.
- */
-#ifdef CONFIG_USER_ONLY
-#define PL0U_R PL0_R
-#else
-#define PL0U_R PL1_R
-#endif
-
-#define PL3_RW (PL3_R | PL3_W)
-#define PL2_RW (PL2_R | PL2_W)
-#define PL1_RW (PL1_R | PL1_W)
-#define PL0_RW (PL0_R | PL0_W)
-
/* Return the highest implemented Exception Level */
static inline int arm_highest_el(CPUARMState *env)
{
@@ -2784,236 +2646,6 @@ static inline int arm_current_el(CPUARMState *env)
}
}
-typedef struct ARMCPRegInfo ARMCPRegInfo;
-
-typedef enum CPAccessResult {
- /* Access is permitted */
- CP_ACCESS_OK = 0,
- /* Access fails due to a configurable trap or enable which would
- * result in a categorized exception syndrome giving information about
- * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
- * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
- * PL1 if in EL0, otherwise to the current EL).
- */
- CP_ACCESS_TRAP = 1,
- /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
- * Note that this is not a catch-all case -- the set of cases which may
- * result in this failure is specifically defined by the architecture.
- */
- CP_ACCESS_TRAP_UNCATEGORIZED = 2,
- /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
- CP_ACCESS_TRAP_EL2 = 3,
- CP_ACCESS_TRAP_EL3 = 4,
- /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
- CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
- CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
-} CPAccessResult;
-
-/* Access functions for coprocessor registers. These cannot fail and
- * may not raise exceptions.
- */
-typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
-typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
- uint64_t value);
-/* Access permission check functions for coprocessor registers. */
-typedef CPAccessResult CPAccessFn(CPUARMState *env,
- const ARMCPRegInfo *opaque,
- bool isread);
-/* Hook function for register reset */
-typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
-
-#define CP_ANY 0xff
-
-/* Definition of an ARM coprocessor register */
-struct ARMCPRegInfo {
- /* Name of register (useful mainly for debugging, need not be unique) */
- const char *name;
- /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
- * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
- * 'wildcard' field -- any value of that field in the MRC/MCR insn
- * will be decoded to this register. The register read and write
- * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
- * used by the program, so it is possible to register a wildcard and
- * then behave differently on read/write if necessary.
- * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
- * must both be zero.
- * For AArch64-visible registers, opc0 is also used.
- * Since there are no "coprocessors" in AArch64, cp is purely used as a
- * way to distinguish (for KVM's benefit) guest-visible system registers
- * from demuxed ones provided to preserve the "no side effects on
- * KVM register read/write from QEMU" semantics. cp==0x13 is guest
- * visible (to match KVM's encoding); cp==0 will be converted to
- * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
- */
- uint8_t cp;
- uint8_t crn;
- uint8_t crm;
- uint8_t opc0;
- uint8_t opc1;
- uint8_t opc2;
- /* Execution state in which this register is visible: ARM_CP_STATE_* */
- int state;
- /* Register type: ARM_CP_* bits/values */
- int type;
- /* Access rights: PL*_[RW] */
- int access;
- /* Security state: ARM_CP_SECSTATE_* bits/values */
- int secure;
- /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
- * this register was defined: can be used to hand data through to the
- * register read/write functions, since they are passed the ARMCPRegInfo*.
- */
- void *opaque;
- /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
- * fieldoffset is non-zero, the reset value of the register.
- */
- uint64_t resetvalue;
- /* Offset of the field in CPUARMState for this register.
- *
- * This is not needed if either:
- * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
- * 2. both readfn and writefn are specified
- */
- ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
-
- /* Offsets of the secure and non-secure fields in CPUARMState for the
- * register if it is banked. These fields are only used during the static
- * registration of a register. During hashing the bank associated
- * with a given security state is copied to fieldoffset which is used from
- * there on out.
- *
- * It is expected that register definitions use either fieldoffset or
- * bank_fieldoffsets in the definition but not both. It is also expected
- * that both bank offsets are set when defining a banked register. This
- * use indicates that a register is banked.
- */
- ptrdiff_t bank_fieldoffsets[2];
-
- /* Function for making any access checks for this register in addition to
- * those specified by the 'access' permissions bits. If NULL, no extra
- * checks required. The access check is performed at runtime, not at
- * translate time.
- */
- CPAccessFn *accessfn;
- /* Function for handling reads of this register. If NULL, then reads
- * will be done by loading from the offset into CPUARMState specified
- * by fieldoffset.
- */
- CPReadFn *readfn;
- /* Function for handling writes of this register. If NULL, then writes
- * will be done by writing to the offset into CPUARMState specified
- * by fieldoffset.
- */
- CPWriteFn *writefn;
- /* Function for doing a "raw" read; used when we need to copy
- * coprocessor state to the kernel for KVM or out for
- * migration. This only needs to be provided if there is also a
- * readfn and it has side effects (for instance clear-on-read bits).
- */
- CPReadFn *raw_readfn;
- /* Function for doing a "raw" write; used when we need to copy KVM
- * kernel coprocessor state into userspace, or for inbound
- * migration. This only needs to be provided if there is also a
- * writefn and it masks out "unwritable" bits or has write-one-to-clear
- * or similar behaviour.
- */
- CPWriteFn *raw_writefn;
- /* Function for resetting the register. If NULL, then reset will be done
- * by writing resetvalue to the field specified in fieldoffset. If
- * fieldoffset is 0 then no reset will be done.
- */
- CPResetFn *resetfn;
-
- /*
- * "Original" writefn and readfn.
- * For ARMv8.1-VHE register aliases, we overwrite the read/write
- * accessor functions of various EL1/EL0 to perform the runtime
- * check for which sysreg should actually be modified, and then
- * forwards the operation. Before overwriting the accessors,
- * the original function is copied here, so that accesses that
- * really do go to the EL1/EL0 version proceed normally.
- * (The corresponding EL2 register is linked via opaque.)
- */
- CPReadFn *orig_readfn;
- CPWriteFn *orig_writefn;
-};
-
-/* Macros which are lvalues for the field in CPUARMState for the
- * ARMCPRegInfo *ri.
- */
-#define CPREG_FIELD32(env, ri) \
- (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
-#define CPREG_FIELD64(env, ri) \
- (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
-
-#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
-
-void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
- const ARMCPRegInfo *regs, void *opaque);
-void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
- const ARMCPRegInfo *regs, void *opaque);
-static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
-{
- define_arm_cp_regs_with_opaque(cpu, regs, 0);
-}
-static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
-{
- define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
-}
-const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
-
-/*
- * Definition of an ARM co-processor register as viewed from
- * userspace. This is used for presenting sanitised versions of
- * registers to userspace when emulating the Linux AArch64 CPU
- * ID/feature ABI (advertised as HWCAP_CPUID).
- */
-typedef struct ARMCPRegUserSpaceInfo {
- /* Name of register */
- const char *name;
-
- /* Is the name actually a glob pattern */
- bool is_glob;
-
- /* Only some bits are exported to user space */
- uint64_t exported_bits;
-
- /* Fixed bits are applied after the mask */
- uint64_t fixed_bits;
-} ARMCPRegUserSpaceInfo;
-
-#define REGUSERINFO_SENTINEL { .name = NULL }
-
-void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
-
-/* CPWriteFn that can be used to implement writes-ignored behaviour */
-void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t value);
-/* CPReadFn that can be used for read-as-zero behaviour */
-uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
-
-/* CPResetFn that does nothing, for use if no reset is required even
- * if fieldoffset is non zero.
- */
-void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
-
-/* Return true if this reginfo struct's field in the cpu state struct
- * is 64 bits wide.
- */
-static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
-{
- return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
-}
-
-static inline bool cp_access_ok(int current_el,
- const ARMCPRegInfo *ri, int isread)
-{
- return (ri->access >> ((current_el * 2) + isread)) & 1;
-}
-
-/* Raw read of a coprocessor register (as needed for migration, etc) */
-uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
-
/**
* write_list_to_cpustate
* @cpu: ARMCPU
@@ -4072,6 +3704,11 @@ static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
}
+static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id)
+{
+ return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8;
+}
+
/*
* 64-bit feature tests via id registers.
*/
@@ -4249,6 +3886,11 @@ static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
}
+static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
+}
+
static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
@@ -4378,6 +4020,11 @@ static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
}
+static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
+}
+
static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
@@ -4461,6 +4108,16 @@ static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
}
+static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
+{
+ return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
+}
+
+static inline bool isar_feature_any_ras(const ARMISARegisters *id)
+{
+ return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
+}
+
/*
* Forward to the above feature tests given an ARMCPU pointer.
*/
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 2974cbc0d3..c841d55d0e 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -34,6 +34,7 @@
#include "hvf_arm.h"
#include "qapi/visitor.h"
#include "hw/qdev-properties.h"
+#include "cpregs.h"
#ifndef CONFIG_USER_ONLY
@@ -90,7 +91,6 @@ static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
{ .name = "L2MERRSR",
.cp = 15, .opc1 = 3, .crm = 15,
.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
- REGINFO_SENTINEL
};
static void aarch64_a57_initfn(Object *obj)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 13d0e9b195..9338088b22 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -18,6 +18,7 @@
#if !defined(CONFIG_USER_ONLY)
#include "hw/boards.h"
#endif
+#include "cpregs.h"
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
@@ -263,7 +264,6 @@ static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- REGINFO_SENTINEL
};
static void cortex_a8_initfn(Object *obj)
@@ -331,7 +331,6 @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
{ .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
- REGINFO_SENTINEL
};
static void cortex_a9_initfn(Object *obj)
@@ -397,7 +396,6 @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
#endif
{ .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- REGINFO_SENTINEL
};
static void cortex_a7_initfn(Object *obj)
@@ -685,7 +683,6 @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
.access = PL1_RW, .type = ARM_CP_CONST },
{ .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
.opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
- REGINFO_SENTINEL
};
static void cortex_r5_initfn(Object *obj)
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index ca1de47511..f5b35cd55f 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -19,8 +19,9 @@
*/
#include "qemu/osdep.h"
#include "cpu.h"
-#include "internals.h"
#include "exec/gdbstub.h"
+#include "internals.h"
+#include "cpregs.h"
typedef struct RegisterSysregXmlParam {
CPUState *cs;
@@ -272,7 +273,7 @@ static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,
static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
gpointer p)
{
- uint32_t ri_key = *(uint32_t *)key;
+ uint32_t ri_key = (uintptr_t)key;
ARMCPRegInfo *ri = value;
RegisterSysregXmlParam *param = (RegisterSysregXmlParam *)p;
GString *s = param->s;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 5a244c3ed9..b4daf4f076 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -36,6 +36,7 @@
#include "exec/cpu_ldst.h"
#include "semihosting/common-semi.h"
#endif
+#include "cpregs.h"
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
#define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */
@@ -213,11 +214,8 @@ bool write_list_to_cpustate(ARMCPU *cpu)
static void add_cpreg_to_list(gpointer key, gpointer opaque)
{
ARMCPU *cpu = opaque;
- uint64_t regidx;
- const ARMCPRegInfo *ri;
-
- regidx = *(uint32_t *)key;
- ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
+ uint32_t regidx = (uintptr_t)key;
+ const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
@@ -229,11 +227,9 @@ static void add_cpreg_to_list(gpointer key, gpointer opaque)
static void count_cpreg(gpointer key, gpointer opaque)
{
ARMCPU *cpu = opaque;
- uint64_t regidx;
const ARMCPRegInfo *ri;
- regidx = *(uint32_t *)key;
- ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
+ ri = g_hash_table_lookup(cpu->cp_regs, key);
if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
cpu->cpreg_array_len++;
@@ -242,8 +238,8 @@ static void count_cpreg(gpointer key, gpointer opaque)
static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
{
- uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
- uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
+ uint64_t aidx = cpreg_to_kvm_id((uintptr_t)a);
+ uint64_t bidx = cpreg_to_kvm_id((uintptr_t)b);
if (aidx > bidx) {
return 1;
@@ -672,7 +668,6 @@ static const ARMCPRegInfo cp_reginfo[] = {
.secure = ARM_CP_SECSTATE_S,
.fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
.resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo not_v8_cp_reginfo[] = {
@@ -701,7 +696,6 @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = {
{ .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
.opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
.type = ARM_CP_NOP | ARM_CP_OVERRIDE },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo not_v6_cp_reginfo[] = {
@@ -710,7 +704,6 @@ static const ARMCPRegInfo not_v6_cp_reginfo[] = {
*/
{ .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
.access = PL1_W, .type = ARM_CP_WFI },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo not_v7_cp_reginfo[] = {
@@ -759,7 +752,6 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
.opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
{ .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
.opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
- REGINFO_SENTINEL
};
static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -888,7 +880,6 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
.crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
.resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read },
- REGINFO_SENTINEL
};
typedef struct pm_event {
@@ -2134,7 +2125,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
{ .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
.writefn = tlbimvaa_write },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo v7mp_cp_reginfo[] = {
@@ -2151,7 +2141,6 @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = {
{ .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
.writefn = tlbimvaa_is_write },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
@@ -2169,7 +2158,6 @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
.writefn = pmovsset_write,
.raw_writefn = raw_write },
- REGINFO_SENTINEL
};
static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -2210,7 +2198,6 @@ static const ARMCPRegInfo t2ee_cp_reginfo[] = {
{ .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
.accessfn = teehbr_access, .resetvalue = 0 },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo v6k_cp_reginfo[] = {
@@ -2242,7 +2229,6 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
.resetvalue = 0 },
- REGINFO_SENTINEL
};
#ifndef CONFIG_USER_ONLY
@@ -3090,7 +3076,6 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
.writefn = gt_sec_cval_write, .raw_writefn = raw_write,
},
- REGINFO_SENTINEL
};
static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -3131,7 +3116,6 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
.access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
.readfn = gt_virt_cnt_read,
},
- REGINFO_SENTINEL
};
#endif
@@ -3495,7 +3479,6 @@ static const ARMCPRegInfo vapa_cp_reginfo[] = {
.access = PL1_W, .accessfn = ats_access,
.writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
#endif
- REGINFO_SENTINEL
};
/* Return basic MPU access permission bits. */
@@ -3618,7 +3601,6 @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]),
.writefn = pmsav7_rgnr_write,
.resetfn = arm_cp_reset_ignore },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
@@ -3669,7 +3651,6 @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
{ .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
.opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
.fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
- REGINFO_SENTINEL
};
static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -3823,7 +3804,6 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
.access = PL1_RW, .accessfn = access_tvm_trvm,
.fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
.resetvalue = 0, },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo vmsa_cp_reginfo[] = {
@@ -3856,7 +3836,6 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
/* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]),
offsetof(CPUARMState, cp15.tcr_el[1])} },
- REGINFO_SENTINEL
};
/* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
@@ -3941,7 +3920,6 @@ static const ARMCPRegInfo omap_cp_reginfo[] = {
{ .name = "C9", .cp = 15, .crn = 9,
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
.type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
- REGINFO_SENTINEL
};
static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -3974,7 +3952,6 @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
{ .name = "XSCALE_UNLOCK_DCACHE",
.cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
.access = PL1_W, .type = ARM_CP_NOP },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
@@ -3988,7 +3965,6 @@ static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
.access = PL1_RW,
.type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
.resetvalue = 0 },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
@@ -3996,7 +3972,6 @@ static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
{ .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
.resetvalue = 0 },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
@@ -4017,7 +3992,6 @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
.access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
{ .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
.access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
@@ -4030,7 +4004,6 @@ static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
{ .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
.resetvalue = (1 << 30) },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo strongarm_cp_reginfo[] = {
@@ -4039,7 +4012,6 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = {
.crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
.access = PL1_RW, .resetvalue = 0,
.type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
- REGINFO_SENTINEL
};
static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -4106,7 +4078,6 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
offsetof(CPUARMState, cp15.ttbr1_ns) },
.writefn = vmsa_ttbr_write, },
- REGINFO_SENTINEL
};
static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -5125,7 +5096,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.access = PL1_RW, .accessfn = access_trap_aa32s_el1,
.writefn = sdcr_write,
.fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
- REGINFO_SENTINEL
};
/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
@@ -5236,7 +5206,6 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
.type = ARM_CP_CONST,
.cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
.access = PL2_RW, .resetvalue = 0 },
- REGINFO_SENTINEL
};
/* Ditto, but for registers which exist in ARMv8 but not v7 */
@@ -5245,7 +5214,6 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
.cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
.access = PL2_RW,
.type = ARM_CP_CONST, .resetvalue = 0 },
- REGINFO_SENTINEL
};
static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
@@ -5678,7 +5646,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
.access = PL2_RW,
.fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
@@ -5688,7 +5655,6 @@ static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
.access = PL2_RW,
.fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2),
.writefn = hcr_writehigh },
- REGINFO_SENTINEL
};
static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -5709,7 +5675,6 @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = {
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2,
.access = PL2_RW, .accessfn = sel2_access,
.fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) },
- REGINFO_SENTINEL
};
static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -5835,7 +5800,6 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
.access = PL3_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vae3_write },
- REGINFO_SENTINEL
};
#ifndef CONFIG_USER_ONLY
@@ -5945,14 +5909,17 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
for (i = 0; i < ARRAY_SIZE(aliases); i++) {
const struct E2HAlias *a = &aliases[i];
- ARMCPRegInfo *src_reg, *dst_reg;
+ ARMCPRegInfo *src_reg, *dst_reg, *new_reg;
+ bool ok;
if (a->feature && !a->feature(&cpu->isar)) {
continue;
}
- src_reg = g_hash_table_lookup(cpu->cp_regs, &a->src_key);
- dst_reg = g_hash_table_lookup(cpu->cp_regs, &a->dst_key);
+ src_reg = g_hash_table_lookup(cpu->cp_regs,
+ (gpointer)(uintptr_t)a->src_key);
+ dst_reg = g_hash_table_lookup(cpu->cp_regs,
+ (gpointer)(uintptr_t)a->dst_key);
g_assert(src_reg != NULL);
g_assert(dst_reg != NULL);
@@ -5964,19 +5931,16 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
g_assert(src_reg->opaque == NULL);
/* Create alias before redirection so we dup the right data. */
- if (a->new_key) {
- ARMCPRegInfo *new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
- uint32_t *new_key = g_memdup(&a->new_key, sizeof(uint32_t));
- bool ok;
+ new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
- new_reg->name = a->new_name;
- new_reg->type |= ARM_CP_ALIAS;
- /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
- new_reg->access &= PL2_RW | PL3_RW;
+ new_reg->name = a->new_name;
+ new_reg->type |= ARM_CP_ALIAS;
+ /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
+ new_reg->access &= PL2_RW | PL3_RW;
- ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
- g_assert(ok);
- }
+ ok = g_hash_table_insert(cpu->cp_regs,
+ (gpointer)(uintptr_t)a->new_key, new_reg);
+ g_assert(ok);
src_reg->opaque = dst_reg;
src_reg->orig_readfn = src_reg->readfn ?: raw_read;
@@ -6121,7 +6085,6 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
.access = PL1_RW, .accessfn = access_tda,
.type = ARM_CP_NOP },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
@@ -6130,7 +6093,6 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
.access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
{ .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
.access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
- REGINFO_SENTINEL
};
/* Return the exception level to which exceptions should be taken
@@ -6616,7 +6578,6 @@ static void define_debug_regs(ARMCPU *cpu)
.fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
.writefn = dbgbcr_write, .raw_writefn = raw_write
},
- REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, dbgregs);
}
@@ -6635,7 +6596,6 @@ static void define_debug_regs(ARMCPU *cpu)
.fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
.writefn = dbgwcr_write, .raw_writefn = raw_write
},
- REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, dbgregs);
}
@@ -6679,10 +6639,10 @@ static void define_pmu_regs(ARMCPU *cpu)
.crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
.access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
.readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
- .accessfn = pmreg_access },
+ .accessfn = pmreg_access_xevcntr },
{ .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
- .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
+ .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr,
.type = ARM_CP_IO,
.readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
.raw_readfn = pmevcntr_rawread,
@@ -6698,7 +6658,6 @@ static void define_pmu_regs(ARMCPU *cpu)
.type = ARM_CP_IO,
.readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
.raw_writefn = pmevtyper_rawwrite },
- REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, pmev_regs);
g_free(pmevcntr_name);
@@ -6716,7 +6675,6 @@ static void define_pmu_regs(ARMCPU *cpu)
.cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
.resetvalue = extract64(cpu->pmceid1, 32, 32) },
- REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, v81_pmu_regs);
}
@@ -6813,7 +6771,6 @@ static const ARMCPRegInfo lor_reginfo[] = {
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
.access = PL1_R, .accessfn = access_lor_ns,
.type = ARM_CP_CONST, .resetvalue = 0 },
- REGINFO_SENTINEL
};
#ifdef TARGET_AARCH64
@@ -6876,7 +6833,6 @@ static const ARMCPRegInfo pauth_reginfo[] = {
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
.access = PL1_RW, .accessfn = access_pauth,
.fieldoffset = offsetof(CPUARMState, keys.apib.hi) },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo tlbirange_reginfo[] = {
@@ -6988,7 +6944,6 @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5,
.access = PL3_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_rvae3_write },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo tlbios_reginfo[] = {
@@ -7060,7 +7015,6 @@ static const ARMCPRegInfo tlbios_reginfo[] = {
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5,
.access = PL3_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vae3is_write },
- REGINFO_SENTINEL
};
static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -7099,7 +7053,6 @@ static const ARMCPRegInfo rndr_reginfo[] = {
.type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO,
.opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1,
.access = PL0_R, .readfn = rndr_readfn },
- REGINFO_SENTINEL
};
#ifndef CONFIG_USER_ONLY
@@ -7135,7 +7088,6 @@ static const ARMCPRegInfo dcpop_reg[] = {
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
.access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
.accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo dcpodp_reg[] = {
@@ -7143,7 +7095,6 @@ static const ARMCPRegInfo dcpodp_reg[] = {
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
.access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
.accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
- REGINFO_SENTINEL
};
#endif /*CONFIG_USER_ONLY*/
@@ -7245,14 +7196,12 @@ static const ARMCPRegInfo mte_reginfo[] = {
{ .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo mte_tco_ro_reginfo[] = {
{ .name = "TCO", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
.type = ARM_CP_CONST, .access = PL0_RW, },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
@@ -7304,7 +7253,6 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
.accessfn = aa64_zva_access,
#endif
},
- REGINFO_SENTINEL
};
#endif
@@ -7350,7 +7298,6 @@ static const ARMCPRegInfo predinv_reginfo[] = {
{ .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
.type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
- REGINFO_SENTINEL
};
static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -7365,7 +7312,6 @@ static const ARMCPRegInfo ccsidr2_reginfo[] = {
.access = PL1_R,
.accessfn = access_aa64_tid2,
.readfn = ccsidr2_read, .type = ARM_CP_NO_RAW },
- REGINFO_SENTINEL
};
static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -7426,7 +7372,6 @@ static const ARMCPRegInfo jazelle_regs[] = {
.cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0,
.accessfn = access_joscr_jmcr,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo vhe_reginfo[] = {
@@ -7491,7 +7436,6 @@ static const ARMCPRegInfo vhe_reginfo[] = {
.access = PL2_RW, .accessfn = e2h_access,
.writefn = gt_virt_cval_write, .raw_writefn = raw_write },
#endif
- REGINFO_SENTINEL
};
#ifndef CONFIG_USER_ONLY
@@ -7504,7 +7448,6 @@ static const ARMCPRegInfo ats1e1_reginfo[] = {
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
.writefn = ats_write64 },
- REGINFO_SENTINEL
};
static const ARMCPRegInfo ats1cp_reginfo[] = {
@@ -7516,7 +7459,6 @@ static const ARMCPRegInfo ats1cp_reginfo[] = {
.cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
.writefn = ats_write },
- REGINFO_SENTINEL
};
#endif
@@ -7538,7 +7480,6 @@ static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = {
.cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
.access = PL2_RW, .type = ARM_CP_CONST,
.resetvalue = 0 },
- REGINFO_SENTINEL
};
void register_cp_regs_for_features(ARMCPU *cpu)
@@ -7645,7 +7586,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
.resetvalue = cpu->isar.id_isar6 },
- REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, v6_idregs);
define_arm_cp_regs(cpu, v6_cp_reginfo);
@@ -7913,10 +7853,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
.resetvalue = cpu->pmceid1 },
- REGINFO_SENTINEL
};
#ifdef CONFIG_USER_ONLY
- ARMCPRegUserSpaceInfo v8_user_idregs[] = {
+ static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
{ .name = "ID_AA64PFR0_EL1",
.exported_bits = 0x000f000f00ff0000,
.fixed_bits = 0x0000000000000011 },
@@ -7943,7 +7882,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.exported_bits = 0x000000f0ffffffff },
{ .name = "ID_AA64ISAR*_EL1_RESERVED",
.is_glob = true },
- REGUSERINFO_SENTINEL
};
modify_arm_cp_regs(v8_idregs, v8_user_idregs);
#endif
@@ -7983,7 +7921,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL2_RW,
.resetvalue = vmpidr_def,
.fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
- REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, vpidr_regs);
define_arm_cp_regs(cpu, el2_cp_reginfo);
@@ -8022,7 +7959,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL2_RW, .accessfn = access_el3_aa32ns,
.type = ARM_CP_NO_RAW,
.writefn = arm_cp_write_ignore, .readfn = mpidr_read },
- REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, vpidr_regs);
define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
@@ -8045,7 +7981,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.raw_writefn = raw_write, .writefn = sctlr_write,
.fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
.resetvalue = cpu->reset_sctlr },
- REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, el3_regs);
@@ -8060,7 +7995,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
*/
if (arm_feature(env, ARM_FEATURE_EL3)) {
if (arm_feature(env, ARM_FEATURE_AARCH64)) {
- ARMCPRegInfo nsacr = {
+ static const ARMCPRegInfo nsacr = {
.name = "NSACR", .type = ARM_CP_CONST,
.cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
.access = PL1_RW, .accessfn = nsacr_access,
@@ -8068,7 +8003,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
};
define_one_arm_cp_reg(cpu, &nsacr);
} else {
- ARMCPRegInfo nsacr = {
+ static const ARMCPRegInfo nsacr = {
.name = "NSACR",
.cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
.access = PL3_RW | PL1_R,
@@ -8079,7 +8014,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
} else {
if (arm_feature(env, ARM_FEATURE_V8)) {
- ARMCPRegInfo nsacr = {
+ static const ARMCPRegInfo nsacr = {
.name = "NSACR", .type = ARM_CP_CONST,
.cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
.access = PL1_R,
@@ -8180,7 +8115,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
{ .name = "DUMMY",
.cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
- REGINFO_SENTINEL
};
ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
{ .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
@@ -8200,7 +8134,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL1_R,
.accessfn = access_aa64_tid1,
.type = ARM_CP_CONST, .resetvalue = cpu->revidr },
- REGINFO_SENTINEL
};
ARMCPRegInfo id_cp_reginfo[] = {
/* These are common to v8 and pre-v8 */
@@ -8218,7 +8151,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL1_R,
.accessfn = access_aa32_tid1,
.type = ARM_CP_CONST, .resetvalue = 0 },
- REGINFO_SENTINEL
};
/* TLBTR is specific to VMSA */
ARMCPRegInfo id_tlbtr_reginfo = {
@@ -8235,35 +8167,33 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->pmsav7_dregion << 8
};
- ARMCPRegInfo crn0_wi_reginfo = {
+ static const ARMCPRegInfo crn0_wi_reginfo = {
.name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
.type = ARM_CP_NOP | ARM_CP_OVERRIDE
};
#ifdef CONFIG_USER_ONLY
- ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
+ static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
{ .name = "MIDR_EL1",
.exported_bits = 0x00000000ffffffff },
{ .name = "REVIDR_EL1" },
- REGUSERINFO_SENTINEL
};
modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
#endif
if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
arm_feature(env, ARM_FEATURE_STRONGARM)) {
- ARMCPRegInfo *r;
+ size_t i;
/* Register the blanket "writes ignored" value first to cover the
* whole space. Then update the specific ID registers to allow write
* access, so that they ignore writes rather than causing them to
* UNDEF.
*/
define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
- for (r = id_pre_v8_midr_cp_reginfo;
- r->type != ARM_CP_SENTINEL; r++) {
- r->access = PL1_RW;
+ for (i = 0; i < ARRAY_SIZE(id_pre_v8_midr_cp_reginfo); ++i) {
+ id_pre_v8_midr_cp_reginfo[i].access = PL1_RW;
}
- for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
- r->access = PL1_RW;
+ for (i = 0; i < ARRAY_SIZE(id_cp_reginfo); ++i) {
+ id_cp_reginfo[i].access = PL1_RW;
}
id_mpuir_reginfo.access = PL1_RW;
id_tlbtr_reginfo.access = PL1_RW;
@@ -8286,13 +8216,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
{ .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
.access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
- REGINFO_SENTINEL
};
#ifdef CONFIG_USER_ONLY
- ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
+ static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
{ .name = "MPIDR_EL1",
.fixed_bits = 0x0000000080000000 },
- REGUSERINFO_SENTINEL
};
modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo);
#endif
@@ -8313,7 +8241,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
.access = PL3_RW, .type = ARM_CP_CONST,
.resetvalue = 0 },
- REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, auxcr_reginfo);
if (cpu_isar_feature(aa32_ac2, cpu)) {
@@ -8348,7 +8275,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.type = ARM_CP_CONST,
.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
.access = PL1_R, .resetvalue = cpu->reset_cbar },
- REGINFO_SENTINEL
};
/* We don't implement a r/w 64 bit CBAR currently */
assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
@@ -8371,14 +8297,13 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
if (arm_feature(env, ARM_FEATURE_VBAR)) {
- ARMCPRegInfo vbar_cp_reginfo[] = {
+ static const ARMCPRegInfo vbar_cp_reginfo[] = {
{ .name = "VBAR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .writefn = vbar_write,
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
offsetof(CPUARMState, cp15.vbar_ns) },
.resetvalue = 0 },
- REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, vbar_cp_reginfo);
}
@@ -8571,27 +8496,81 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
return cpu_list;
}
+/*
+ * Private utility function for define_one_arm_cp_reg_with_opaque():
+ * add a single reginfo struct to the hash table.
+ */
static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
- void *opaque, int state, int secstate,
+ void *opaque, CPState state,
+ CPSecureState secstate,
int crm, int opc1, int opc2,
const char *name)
{
- /* Private utility function for define_one_arm_cp_reg_with_opaque():
- * add a single reginfo struct to the hash table.
- */
- uint32_t *key = g_new(uint32_t, 1);
- ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
- int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
- int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
+ uint32_t key;
+ ARMCPRegInfo *r2;
+ bool is64 = r->type & ARM_CP_64BIT;
+ bool ns = secstate & ARM_CP_SECSTATE_NS;
+ int cp = r->cp;
+ bool isbanked;
+ size_t name_len;
+
+ switch (state) {
+ case ARM_CP_STATE_AA32:
+ /* We assume it is a cp15 register if the .cp field is left unset. */
+ if (cp == 0 && r->state == ARM_CP_STATE_BOTH) {
+ cp = 15;
+ }
+ key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2);
+ break;
+ case ARM_CP_STATE_AA64:
+ /*
+ * To allow abbreviation of ARMCPRegInfo definitions, we treat
+ * cp == 0 as equivalent to the value for "standard guest-visible
+ * sysreg". STATE_BOTH definitions are also always "standard sysreg"
+ * in their AArch64 view (the .cp value may be non-zero for the
+ * benefit of the AArch32 view).
+ */
+ if (cp == 0 || r->state == ARM_CP_STATE_BOTH) {
+ cp = CP_REG_ARM64_SYSREG_CP;
+ }
+ key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ /* Overriding of an existing definition must be explicitly requested. */
+ if (!(r->type & ARM_CP_OVERRIDE)) {
+ const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key);
+ if (oldreg) {
+ assert(oldreg->type & ARM_CP_OVERRIDE);
+ }
+ }
+
+ /* Combine cpreg and name into one allocation. */
+ name_len = strlen(name) + 1;
+ r2 = g_malloc(sizeof(*r2) + name_len);
+ *r2 = *r;
+ r2->name = memcpy(r2 + 1, name, name_len);
- r2->name = g_strdup(name);
- /* Reset the secure state to the specific incoming state. This is
- * necessary as the register may have been defined with both states.
+ /*
+ * Update fields to match the instantiation, overwiting wildcards
+ * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
*/
+ r2->cp = cp;
+ r2->crm = crm;
+ r2->opc1 = opc1;
+ r2->opc2 = opc2;
+ r2->state = state;
r2->secure = secstate;
+ if (opaque) {
+ r2->opaque = opaque;
+ }
- if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
- /* Register is banked (using both entries in array).
+ isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
+ if (isbanked) {
+ /*
+ * Register is banked (using both entries in array).
* Overwriting fieldoffset as the array is only used to define
* banked registers but later only fieldoffset is used.
*/
@@ -8599,8 +8578,9 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
}
if (state == ARM_CP_STATE_AA32) {
- if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
- /* If the register is banked then we don't need to migrate or
+ if (isbanked) {
+ /*
+ * If the register is banked then we don't need to migrate or
* reset the 32-bit instance in certain cases:
*
* 1) If the register has both 32-bit and 64-bit instances then we
@@ -8615,62 +8595,27 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
r2->type |= ARM_CP_ALIAS;
}
} else if ((secstate != r->secure) && !ns) {
- /* The register is not banked so we only want to allow migration of
- * the non-secure instance.
+ /*
+ * The register is not banked so we only want to allow migration
+ * of the non-secure instance.
*/
r2->type |= ARM_CP_ALIAS;
}
- if (r->state == ARM_CP_STATE_BOTH) {
- /* We assume it is a cp15 register if the .cp field is left unset.
- */
- if (r2->cp == 0) {
- r2->cp = 15;
- }
-
-#if HOST_BIG_ENDIAN
- if (r2->fieldoffset) {
- r2->fieldoffset += sizeof(uint32_t);
- }
-#endif
- }
- }
- if (state == ARM_CP_STATE_AA64) {
- /* To allow abbreviation of ARMCPRegInfo
- * definitions, we treat cp == 0 as equivalent to
- * the value for "standard guest-visible sysreg".
- * STATE_BOTH definitions are also always "standard
- * sysreg" in their AArch64 view (the .cp value may
- * be non-zero for the benefit of the AArch32 view).
- */
- if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
- r2->cp = CP_REG_ARM64_SYSREG_CP;
+ if (HOST_BIG_ENDIAN &&
+ r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
+ r2->fieldoffset += sizeof(uint32_t);
}
- *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
- r2->opc0, opc1, opc2);
- } else {
- *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
}
- if (opaque) {
- r2->opaque = opaque;
- }
- /* reginfo passed to helpers is correct for the actual access,
- * and is never ARM_CP_STATE_BOTH:
- */
- r2->state = state;
- /* Make sure reginfo passed to helpers for wildcarded regs
- * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
- */
- r2->crm = crm;
- r2->opc1 = opc1;
- r2->opc2 = opc2;
- /* By convention, for wildcarded registers only the first
+
+ /*
+ * By convention, for wildcarded registers only the first
* entry is used for migration; the others are marked as
* ALIAS so we don't try to transfer the register
* multiple times. Special registers (ie NOP/WFI) are
* never migratable and not even raw-accessible.
*/
- if ((r->type & ARM_CP_SPECIAL)) {
+ if (r->type & ARM_CP_SPECIAL_MASK) {
r2->type |= ARM_CP_NO_RAW;
}
if (((r->crm == CP_ANY) && crm != 0) ||
@@ -8679,7 +8624,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
}
- /* Check that raw accesses are either forbidden or handled. Note that
+ /*
+ * Check that raw accesses are either forbidden or handled. Note that
* we can't assert this earlier because the setup of fieldoffset for
* banked registers has to be done first.
*/
@@ -8687,22 +8633,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
assert(!raw_accessors_invalid(r2));
}
- /* Overriding of an existing definition must be explicitly
- * requested.
- */
- if (!(r->type & ARM_CP_OVERRIDE)) {
- ARMCPRegInfo *oldreg;
- oldreg = g_hash_table_lookup(cpu->cp_regs, key);
- if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
- fprintf(stderr, "Register redefined: cp=%d %d bit "
- "crn=%d crm=%d opc1=%d opc2=%d, "
- "was %s, now %s\n", r2->cp, 32 + 32 * is64,
- r2->crn, r2->crm, r2->opc1, r2->opc2,
- oldreg->name, r2->name);
- g_assert_not_reached();
- }
- }
- g_hash_table_insert(cpu->cp_regs, key, r2);
+ g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2);
}
@@ -8732,13 +8663,15 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
* bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
* the register, if any.
*/
- int crm, opc1, opc2, state;
+ int crm, opc1, opc2;
int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
+ CPState state;
+
/* 64 bit registers have only CRm and Opc1 fields */
assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
/* op0 only exists in the AArch64 encodings */
@@ -8781,7 +8714,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
* to encompass the generic architectural permission check.
*/
if (r->state != ARM_CP_STATE_AA32) {
- int mask = 0;
+ CPAccessRights mask;
switch (r->opc1) {
case 0:
/* min_EL EL1, but some accessible to EL0 via kernel ABI */
@@ -8810,8 +8743,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
break;
default:
/* broken reginfo with out-of-range opc1 */
- assert(false);
- break;
+ g_assert_not_reached();
}
/* assert our permissions are not too lax (stricter is fine) */
assert((r->access & ~mask) == 0);
@@ -8820,7 +8752,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
/* Check that the register definition has enough info to handle
* reads and writes if they are permitted.
*/
- if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
+ if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) {
if (r->access & PL3_R) {
assert((r->fieldoffset ||
(r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
@@ -8832,8 +8764,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
r->writefn);
}
}
- /* Bad type field probably means missing sentinel at end of reg list */
- assert(cptype_valid(r->type));
+
for (crm = crmmin; crm <= crmmax; crm++) {
for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
@@ -8855,7 +8786,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
r->secure, crm, opc1, opc2,
r->name);
break;
- default:
+ case ARM_CP_SECSTATE_BOTH:
name = g_strdup_printf("%s_S", r->name);
add_cpreg_to_hashtable(cpu, r, opaque, state,
ARM_CP_SECSTATE_S,
@@ -8865,6 +8796,8 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
ARM_CP_SECSTATE_NS,
crm, opc1, opc2, r->name);
break;
+ default:
+ g_assert_not_reached();
}
} else {
/* AArch64 registers get mapped to non-secure instance
@@ -8879,13 +8812,13 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
}
}
-void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
- const ARMCPRegInfo *regs, void *opaque)
+/* Define a whole list of registers */
+void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs,
+ void *opaque, size_t len)
{
- /* Define a whole list of registers */
- const ARMCPRegInfo *r;
- for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
- define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
+ size_t i;
+ for (i = 0; i < len; ++i) {
+ define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque);
}
}
@@ -8897,17 +8830,20 @@ void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
* user-space cannot alter any values and dynamic values pertaining to
* execution state are hidden from user space view anyway.
*/
-void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods)
+void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
+ const ARMCPRegUserSpaceInfo *mods,
+ size_t mods_len)
{
- const ARMCPRegUserSpaceInfo *m;
- ARMCPRegInfo *r;
-
- for (m = mods; m->name; m++) {
+ for (size_t mi = 0; mi < mods_len; ++mi) {
+ const ARMCPRegUserSpaceInfo *m = mods + mi;
GPatternSpec *pat = NULL;
+
if (m->is_glob) {
pat = g_pattern_spec_new(m->name);
}
- for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
+ for (size_t ri = 0; ri < regs_len; ++ri) {
+ ARMCPRegInfo *r = regs + ri;
+
if (pat && g_pattern_match_string(pat, r->name)) {
r->type = ARM_CP_CONST;
r->access = PL0U_R;
@@ -8929,7 +8865,7 @@ void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods)
const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
{
- return g_hash_table_lookup(cpregs, &encoded_cp);
+ return g_hash_table_lookup(cpregs, (gpointer)(uintptr_t)encoded_cp);
}
void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -10891,7 +10827,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
break;
default:
/* Never happens, but compiler isn't smart enough to tell. */
- abort();
+ g_assert_not_reached();
}
}
*prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
@@ -11012,7 +10948,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
break;
default:
/* Never happens, but compiler isn't smart enough to tell. */
- abort();
+ g_assert_not_reached();
}
}
if (domain_prot == 3) {
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index b11a8b9a18..86710509d2 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -1200,7 +1200,7 @@ int hvf_vcpu_exec(CPUState *cpu)
/* we got kicked, no exit to process */
return 0;
default:
- assert(0);
+ g_assert_not_reached();
}
hvf_sync_vtimer(cpu);
diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c
index 56a7099e6b..965a486b32 100644
--- a/target/arm/kvm-stub.c
+++ b/target/arm/kvm-stub.c
@@ -15,10 +15,10 @@
bool write_kvmstate_to_list(ARMCPU *cpu)
{
- abort();
+ g_assert_not_reached();
}
bool write_list_to_kvmstate(ARMCPU *cpu, int level)
{
- abort();
+ g_assert_not_reached();
}
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 5fc37ac10a..4339e1cd6e 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -540,7 +540,7 @@ bool write_kvmstate_to_list(ARMCPU *cpu)
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
break;
default:
- abort();
+ g_assert_not_reached();
}
if (ret) {
ok = false;
@@ -575,7 +575,7 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
r.addr = (uintptr_t)(cpu->cpreg_values + i);
break;
default:
- abort();
+ g_assert_not_reached();
}
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
if (ret) {
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 135d2420b5..285e387d2c 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -661,7 +661,7 @@ static int cpu_pre_save(void *opaque)
if (kvm_enabled()) {
if (!write_kvmstate_to_list(cpu)) {
/* This should never fail */
- abort();
+ g_assert_not_reached();
}
/*
@@ -672,7 +672,7 @@ static int cpu_pre_save(void *opaque)
} else {
if (!write_cpustate_to_list(cpu, false)) {
/* This should never fail. */
- abort();
+ g_assert_not_reached();
}
}
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 2b87e8808b..76499ffa14 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -23,6 +23,7 @@
#include "internals.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
+#include "cpregs.h"
#define SIGNBIT (uint32_t)0x80000000
#define SIGNBIT64 ((uint64_t)1 << 63)
@@ -631,11 +632,13 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
uint32_t isread)
{
const ARMCPRegInfo *ri = rip;
+ CPAccessResult res = CP_ACCESS_OK;
int target_el;
if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14
&& extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) {
- raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env));
+ res = CP_ACCESS_TRAP;
+ goto fail;
}
/*
@@ -654,48 +657,46 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
mask &= ~((1 << 4) | (1 << 14));
if (env->cp15.hstr_el2 & mask) {
- target_el = 2;
- goto exept;
+ res = CP_ACCESS_TRAP_EL2;
+ goto fail;
}
}
- if (!ri->accessfn) {
+ if (ri->accessfn) {
+ res = ri->accessfn(env, ri, isread);
+ }
+ if (likely(res == CP_ACCESS_OK)) {
return;
}
- switch (ri->accessfn(env, ri, isread)) {
- case CP_ACCESS_OK:
- return;
+ fail:
+ switch (res & ~CP_ACCESS_EL_MASK) {
case CP_ACCESS_TRAP:
- target_el = exception_target_el(env);
- break;
- case CP_ACCESS_TRAP_EL2:
- /* Requesting a trap to EL2 when we're in EL3 is
- * a bug in the access function.
- */
- assert(arm_current_el(env) != 3);
- target_el = 2;
- break;
- case CP_ACCESS_TRAP_EL3:
- target_el = 3;
break;
case CP_ACCESS_TRAP_UNCATEGORIZED:
- target_el = exception_target_el(env);
syndrome = syn_uncategorized();
break;
- case CP_ACCESS_TRAP_UNCATEGORIZED_EL2:
- target_el = 2;
- syndrome = syn_uncategorized();
+ default:
+ g_assert_not_reached();
+ }
+
+ target_el = res & CP_ACCESS_EL_MASK;
+ switch (target_el) {
+ case 0:
+ target_el = exception_target_el(env);
break;
- case CP_ACCESS_TRAP_UNCATEGORIZED_EL3:
- target_el = 3;
- syndrome = syn_uncategorized();
+ case 2:
+ assert(arm_current_el(env) != 3);
+ assert(arm_is_el2_enabled(env));
+ break;
+ case 3:
+ assert(arm_feature(env, ARM_FEATURE_EL3));
break;
default:
+ /* No "direct" traps to EL1 */
g_assert_not_reached();
}
-exept:
raise_exception(env, EXCP_UDEF, syndrome, target_el);
}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index a869d57309..b80313670f 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -27,14 +27,12 @@
#include "translate.h"
#include "internals.h"
#include "qemu/host-utils.h"
-
#include "semihosting/semihost.h"
#include "exec/gen-icount.h"
-
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
#include "exec/log.h"
-
+#include "cpregs.h"
#include "translate-a64.h"
#include "qemu/atomic128.h"
@@ -1835,7 +1833,9 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
}
/* Handle special cases first */
- switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
+ switch (ri->type & ARM_CP_SPECIAL_MASK) {
+ case 0:
+ break;
case ARM_CP_NOP:
return;
case ARM_CP_NZCV:
@@ -1910,7 +1910,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
}
return;
default:
- break;
+ g_assert_not_reached();
}
if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) {
return;
@@ -6151,7 +6151,7 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
break;
default:
- abort();
+ g_assert_not_reached();
}
write_fp_sreg(s, rd, tcg_res);
@@ -6392,7 +6392,7 @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
break;
}
default:
- abort();
+ g_assert_not_reached();
}
}
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index 2e4d1ec87d..321c17e2c7 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -679,7 +679,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
}
break;
default:
- abort();
+ g_assert_not_reached();
}
if ((vd + a->stride * (nregs - 1)) > 31) {
/*
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 37fb17cdaa..4e19191ed5 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -30,11 +30,10 @@
#include "qemu/bitops.h"
#include "arm_ldst.h"
#include "semihosting/semihost.h"
-
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
-
#include "exec/log.h"
+#include "cpregs.h"
#define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T)
@@ -4745,7 +4744,9 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
}
/* Handle special cases first */
- switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
+ switch (ri->type & ARM_CP_SPECIAL_MASK) {
+ case 0:
+ break;
case ARM_CP_NOP:
return;
case ARM_CP_WFI:
@@ -4757,7 +4758,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
s->base.is_jmp = DISAS_WFI;
return;
default:
- break;
+ g_assert_not_reached();
}
if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
@@ -5155,7 +5156,7 @@ static void gen_srs(DisasContext *s,
offset = 4;
break;
default:
- abort();
+ g_assert_not_reached();
}
tcg_gen_addi_i32(addr, addr, offset);
tmp = load_reg(s, 14);
@@ -5180,7 +5181,7 @@ static void gen_srs(DisasContext *s,
offset = 0;
break;
default:
- abort();
+ g_assert_not_reached();
}
tcg_gen_addi_i32(addr, addr, offset);
gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr);
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index 6ad0ad49f9..d6a74d24dc 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -28,9 +28,9 @@ endif
# BTI Tests
# bti-1 tests the elf notes, so we require special compiler support.
ifneq ($(CROSS_CC_HAS_ARMV8_BTI),)
-AARCH64_TESTS += bti-1
-bti-1: CFLAGS += -mbranch-protection=standard
-bti-1: LDFLAGS += -nostdlib
+AARCH64_TESTS += bti-1 bti-3
+bti-1 bti-3: CFLAGS += -mbranch-protection=standard
+bti-1 bti-3: LDFLAGS += -nostdlib
endif
# bti-2 tests PROT_BTI, so no special compiler support required.
AARCH64_TESTS += bti-2
diff --git a/tests/tcg/aarch64/bti-3.c b/tests/tcg/aarch64/bti-3.c
new file mode 100644
index 0000000000..a852856d9a
--- /dev/null
+++ b/tests/tcg/aarch64/bti-3.c
@@ -0,0 +1,42 @@
+/*
+ * BTI vs PACIASP
+ */
+
+#include "bti-crt.inc.c"
+
+static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc)
+{
+ uc->uc_mcontext.pc += 8;
+ uc->uc_mcontext.pstate = 1;
+}
+
+#define BTYPE_1() \
+ asm("mov %0,#1; adr x16, 1f; br x16; 1: hint #25; mov %0,#0" \
+ : "=r"(skipped) : : "x16", "x30")
+
+#define BTYPE_2() \
+ asm("mov %0,#1; adr x16, 1f; blr x16; 1: hint #25; mov %0,#0" \
+ : "=r"(skipped) : : "x16", "x30")
+
+#define BTYPE_3() \
+ asm("mov %0,#1; adr x15, 1f; br x15; 1: hint #25; mov %0,#0" \
+ : "=r"(skipped) : : "x15", "x30")
+
+#define TEST(WHICH, EXPECT) \
+ do { WHICH(); fail += skipped ^ EXPECT; } while (0)
+
+int main()
+{
+ int fail = 0;
+ int skipped;
+
+ /* Signal-like with SA_SIGINFO. */
+ signal_info(SIGILL, skip2_sigill);
+
+ /* With SCTLR_EL1.BT0 set, PACIASP is not compatible with type=3. */
+ TEST(BTYPE_1, 0);
+ TEST(BTYPE_2, 0);
+ TEST(BTYPE_3, 1);
+
+ return fail;
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-27 04:37:47 +0000