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authorPeter Maydell <peter.maydell@linaro.org>2010-12-07 15:37:34 +0000
committerPeter Maydell <peter.maydell@linaro.org>2010-12-07 15:37:34 +0000
commitf73534a56e21f0fa37c10941a2a887b3576c2f69 (patch)
treed145ef924dcfdb847219fa3ba51f97bfcfee1422
parent04595bf66f15cb205cb7f64eaa3a38804bf0893a (diff)
downloadqemu-arm-f73534a56e21f0fa37c10941a2a887b3576c2f69.tar.gz
ARM: Fix decoding of Neon forms of VCVT between float and fixed point
Fix errors in the decoding of the Neon forms of fixed-point VCVT: * fixed-point VCVT is op 14 and 15, not 15 and 16 * the fbits immediate field was being misinterpreted * the sense of the to_fixed bit was inverted Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
-rw-r--r--target-arm/translate.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 69a424aa50..0b3e4e6c6a 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -4850,11 +4850,15 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
}
neon_store_reg64(cpu_V0, rd + pass);
}
- } else if (op == 15 || op == 16) {
+ } else if (op >= 14) {
/* VCVT fixed-point. */
+ /* We have already masked out the must-be-1 top bit of imm6,
+ * hence this 32-shift where the ARM ARM has 64-imm6.
+ */
+ shift = 32 - shift;
for (pass = 0; pass < (q ? 4 : 2); pass++) {
tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
- if (op & 1) {
+ if (!(op & 1)) {
if (u)
gen_vfp_ulto(0, shift);
else