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authorPeter Maydell <peter.maydell@linaro.org>2010-12-07 15:37:34 +0000
committerPeter Maydell <peter.maydell@linaro.org>2010-12-07 15:37:34 +0000
commit2d6277373d3fc18f11504cd05ea82f0fe6d67962 (patch)
tree79cd0a50165399bf9f87890e1a1965363304d682
parentb408dbdec3d3220b7e2da2b0fd768048f43a2e39 (diff)
downloadqemu-arm-2d6277373d3fc18f11504cd05ea82f0fe6d67962.tar.gz
ARM: Return correct result for single<->double conversion of NaN
The ARM ARM defines that if the input to a single<->double conversion is a NaN then the output is always forced to be a quiet NaN by setting the most significant bit of the fraction part. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
-rw-r--r--target-arm/helper.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6d2a8f2ad9..4bd1cd4fa4 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2528,12 +2528,20 @@ float32 VFP_HELPER(tosiz, d)(float64 x, CPUState *env)
/* floating point conversion */
float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
{
- return float32_to_float64(x, &env->vfp.fp_status);
+ float64 r = float32_to_float64(x, &env->vfp.fp_status);
+ /* ARM requires that S<->D conversion of any kind of NaN generates
+ * a quiet NaN by forcing the most significant frac bit to 1.
+ */
+ return float64_maybe_silence_nan(r);
}
float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env)
{
- return float64_to_float32(x, &env->vfp.fp_status);
+ float32 r = float64_to_float32(x, &env->vfp.fp_status);
+ /* ARM requires that S<->D conversion of any kind of NaN generates
+ * a quiet NaN by forcing the most significant frac bit to 1.
+ */
+ return float32_maybe_silence_nan(r);
}
/* VFP3 fixed point conversion. */