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authorPeter Maydell <peter.maydell@linaro.org>2018-04-10 13:02:25 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-04-10 13:02:25 +0100
commit8aec759b45fa6986c0b159cb27353d6abb0d5d73 (patch)
treed936e8765267e8be307c6b79d1d085d9f76c0958
parentf640a5914f5179aa1af00df70da470e24e055e8d (diff)
downloadqemu-arm-8aec759b45fa6986c0b159cb27353d6abb0d5d73.tar.gz
target/arm: Report unsupported MPU region sizes more clearly
Currently our PMSAv7 and ARMv7M MPU implementation cannot handle MPU region sizes smaller than our TARGET_PAGE_SIZE. However we report that in a slightly confusing way: DRSR[3]: No support for MPU (sub)region alignment of 9 bits. Minimum is 10 The problem is not the alignment of the region, but its size; tweak the error message to say so: DRSR[3]: No support for MPU (sub)region size of 512 bytes. Minimum is 1024. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180405172554.27401-1-peter.maydell@linaro.org
-rw-r--r--target/arm/helper.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c
index dcb8476d9e..b14fdab140 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9625,9 +9625,9 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
}
if (rsize < TARGET_PAGE_BITS) {
qemu_log_mask(LOG_UNIMP,
- "DRSR[%d]: No support for MPU (sub)region "
- "alignment of %" PRIu32 " bits. Minimum is %d\n",
- n, rsize, TARGET_PAGE_BITS);
+ "DRSR[%d]: No support for MPU (sub)region size of"
+ " %" PRIu32 " bytes. Minimum is %d.\n",
+ n, (1 << rsize), TARGET_PAGE_SIZE);
continue;
}
if (srdis) {