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authorPeter Maydell <peter.maydell@linaro.org>2018-04-10 14:42:03 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-04-11 17:00:49 +0100
commit6670b494fdb23f74ecd9be3d952c007f64e268f1 (patch)
tree79b7373bbae600f3cc6992d171d99f6f2a870d6d
parent6523eaca378df1455481f1cec65ada589d65df0e (diff)
downloadqemu-arm-6670b494fdb23f74ecd9be3d952c007f64e268f1.tar.gz
hw/char/cmsdk-apb-uart.c: Correctly clear INTSTATUS bits on writes
The CMSDK APB UART INTSTATUS register bits are all write-one-to-clear. We were getting this correct for the TXO and RXO bits (which need special casing because their state lives in the STATE register), but had forgotten to handle the normal bits for RX and TX which we do store in our s->intstatus field. Perform the W1C operation on the bits in s->intstatus too. Fixes: https://bugs.launchpad.net/qemu/+bug/1760262 Cc: qemu-stable@nongnu.org Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180410134203.17552-1-peter.maydell@linaro.org
-rw-r--r--hw/char/cmsdk-apb-uart.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/char/cmsdk-apb-uart.c b/hw/char/cmsdk-apb-uart.c
index 1ad1e14295..9c0929d8a2 100644
--- a/hw/char/cmsdk-apb-uart.c
+++ b/hw/char/cmsdk-apb-uart.c
@@ -274,6 +274,7 @@ static void uart_write(void *opaque, hwaddr offset, uint64_t value,
* is then reflected into the intstatus value by the update function).
*/
s->state &= ~(value & (R_INTSTATUS_TXO_MASK | R_INTSTATUS_RXO_MASK));
+ s->intstatus &= ~value;
cmsdk_apb_uart_update(s);
break;
case A_BAUDDIV: