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authorJames Cowgill <james.cowgill@mips.com>2018-03-15 15:13:48 +0000
committerLaurent Vivier <laurent@vivier.eu>2018-04-10 18:00:14 +0200
commit46a1ee4f397ffd305da95fb65dc73be49667ff6d (patch)
tree918987b241ace69c94e6876e6db70905c1a24067
parent947aeab311adcaac1e082ddcf811504ea54529a5 (diff)
downloadqemu-arm-46a1ee4f397ffd305da95fb65dc73be49667ff6d.tar.gz
linux-user: implement HWCAP bits on MIPS
Add support for the two currently defined HWCAP bits on MIPS - R6 and MSA. Buglink: https://bugs.launchpad.net/qemu/+bug/1754372 Signed-off-by: James Cowgill <james.cowgill@mips.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180315151348.6451-1-james.cowgill@mips.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
-rw-r--r--linux-user/elfload.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 23e34957f9..c77ed1bb01 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -882,6 +882,30 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMIPSState *e
#define USE_ELF_CORE_DUMP
#define ELF_EXEC_PAGESIZE 4096
+/* See arch/mips/include/uapi/asm/hwcap.h. */
+enum {
+ HWCAP_MIPS_R6 = (1 << 0),
+ HWCAP_MIPS_MSA = (1 << 1),
+};
+
+#define ELF_HWCAP get_elf_hwcap()
+
+static uint32_t get_elf_hwcap(void)
+{
+ MIPSCPU *cpu = MIPS_CPU(thread_cpu);
+ uint32_t hwcaps = 0;
+
+#define GET_FEATURE(flag, hwcap) \
+ do { if (cpu->env.insn_flags & (flag)) { hwcaps |= hwcap; } } while (0)
+
+ GET_FEATURE(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6);
+ GET_FEATURE(ASE_MSA, HWCAP_MIPS_MSA);
+
+#undef GET_FEATURE
+
+ return hwcaps;
+}
+
#endif /* TARGET_MIPS */
#ifdef TARGET_MICROBLAZE