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authorPeter Maydell <peter.maydell@linaro.org>2014-08-18 10:41:27 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-08-18 10:41:27 +0100
commite4327b0d49bbd8e79c9d1f220804cc712a759836 (patch)
tree799004a3d6c0c38f23e992fd05900717a5bc94e4
parent2ee55b8351910e5dd898f52415064a4c5479baba (diff)
downloadqemu-arm-e4327b0d49bbd8e79c9d1f220804cc712a759836.tar.gz
target-arm: Fix return address for A64 BRK instructions
When we take an exception resulting from a BRK instruction, the architecture requires that the "preferred return address" reported to the exception handler is the address of the BRK itself, not the following instruction (like undefined insns, and in contrast with SVC, HVC and SMC). Follow this, rather than incorrectly reporting the address of the following insn. (We do get this correct for the A32/T32 BKPT insns.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/translate-a64.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 33b5025fee..fc319d5b2f 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1454,7 +1454,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
break;
}
/* BRK */
- gen_exception_insn(s, 0, EXCP_BKPT, syn_aa64_bkpt(imm16));
+ gen_exception_insn(s, 4, EXCP_BKPT, syn_aa64_bkpt(imm16));
break;
case 2:
if (op2_ll != 0) {