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authorPeter Maydell <peter.maydell@linaro.org>2014-08-07 18:42:03 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-08-18 12:17:57 +0100
commit5ec0d125aaf77190df06c5e80117128129adb1a9 (patch)
tree8b102d7bda12288342270876b8c925b42c0f9954
parentabe78e93d85daf9b8697fcd84a9b636df8c056f4 (diff)
downloadqemu-arm-5ec0d125aaf77190df06c5e80117128129adb1a9.tar.gz
target-arm: Correctly handle PSTATE.SS when taking exception to AArch32
When an exception is taken to AArch32, we must clear the PSTATE.SS bit for the exception handler, and must also ensure that the SS bit is not set in the value saved to SPSR_<mode>. Achieve both of these aims by clearing the bit in uncached_cpsr before saving it to the SPSR. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/helper.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 22bf6d3f68..f981569ae2 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3550,6 +3550,10 @@ void arm_cpu_do_interrupt(CPUState *cs)
addr += env->cp15.vbar_el[1];
}
switch_mode (env, new_mode);
+ /* For exceptions taken to AArch32 we must clear the SS bit in both
+ * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
+ */
+ env->uncached_cpsr &= ~PSTATE_SS;
env->spsr = cpsr_read(env);
/* Clear IT bits. */
env->condexec_bits = 0;