diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2014-05-29 18:17:15 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-05-29 18:49:48 +0100 |
| commit | fcbfba192e7f69b2cb47c9d98f16e089332ac99f (patch) | |
| tree | 3d1fd3be46e77357c1eecd9bf99e71b0af789263 | |
| parent | 12d4617ead8bf8861f910f2a958addfedb688c36 (diff) | |
target-arm: Allow 3reg_wide undefreq to encode more bad size options
The current undefreq field in the neon_3reg_wide handling allows us
to encode "UNDEF if size != 0" and "UNDEF if size == 0". This is
no longer sufficient with the advent of 64-bit polynomial VMULL,
which means we want to UNDEF if size == 1. Change the undefreq
encoding to use separate bits for all of "UNDEF if size == 0",
"UNDEF if size == 1" and "UNDEF if size == 2".
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target-arm/translate.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index ab3713df1c..b79209b537 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -5953,10 +5953,11 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins int src1_wide; int src2_wide; int prewiden; - /* undefreq: bit 0 : UNDEF if size != 0 - * bit 1 : UNDEF if size == 0 - * bit 2 : UNDEF if U == 1 - * Note that [1:0] set implies 'always UNDEF' + /* undefreq: bit 0 : UNDEF if size == 0 + * bit 1 : UNDEF if size == 1 + * bit 2 : UNDEF if size == 2 + * bit 3 : UNDEF if U == 1 + * Note that [2:0] set implies 'always UNDEF' */ int undefreq; /* prewiden, src1_wide, src2_wide, undefreq */ @@ -5970,13 +5971,13 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins {0, 1, 1, 0}, /* VSUBHN */ {0, 0, 0, 0}, /* VABDL */ {0, 0, 0, 0}, /* VMLAL */ - {0, 0, 0, 6}, /* VQDMLAL */ + {0, 0, 0, 9}, /* VQDMLAL */ {0, 0, 0, 0}, /* VMLSL */ - {0, 0, 0, 6}, /* VQDMLSL */ + {0, 0, 0, 9}, /* VQDMLSL */ {0, 0, 0, 0}, /* Integer VMULL */ - {0, 0, 0, 2}, /* VQDMULL */ - {0, 0, 0, 5}, /* Polynomial VMULL */ - {0, 0, 0, 3}, /* Reserved: always UNDEF */ + {0, 0, 0, 1}, /* VQDMULL */ + {0, 0, 0, 15}, /* Polynomial VMULL */ + {0, 0, 0, 7}, /* Reserved: always UNDEF */ }; prewiden = neon_3reg_wide[op][0]; @@ -5984,9 +5985,8 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins src2_wide = neon_3reg_wide[op][2]; undefreq = neon_3reg_wide[op][3]; - if (((undefreq & 1) && (size != 0)) || - ((undefreq & 2) && (size == 0)) || - ((undefreq & 4) && u)) { + if ((undefreq & (1 << size)) || + ((undefreq & 8) && u)) { return 1; } if ((src1_wide && (rn & 1)) || |