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authorPeter Maydell <peter.maydell@linaro.org>2012-03-20 17:25:53 +0000
committerPeter Maydell <peter.maydell@linaro.org>2012-03-23 13:42:33 +0000
commitcb08c4a079e7fb4be603f95ada8ae07e24e5b9a2 (patch)
treef42bb35f43a39969f01bb55d4b99cdcbfbef3099
parent4a652713d1c0f0d8bef0a7238de706943c08491b (diff)
downloadqemu-arm-cb08c4a079e7fb4be603f95ada8ae07e24e5b9a2.tar.gz
target-arm: Convert TLS registers
Convert TLS registers to the new cp15 framework Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/helper.c19
-rw-r--r--target-arm/translate.c58
2 files changed, 19 insertions, 58 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d5cea2d3e8..354d24bcb2 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -309,6 +309,22 @@ static const ARMCPRegInfo t2ee_cp_reginfo[] = {
REGINFO_SENTINEL
};
+static const ARMCPRegInfo v6k_cp_reginfo[] = {
+ { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
+ .access = PL0_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.c13_tls1),
+ .resetvalue = 0 },
+ { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
+ .access = PL0_R|PL1_W,
+ .fieldoffset = offsetof(CPUARMState, cp15.c13_tls2),
+ .resetvalue = 0 },
+ { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
+ .access = PL1_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.c13_tls3),
+ .resetvalue = 0 },
+ REGINFO_SENTINEL
+};
+
void register_cp_regs_for_features(ARMCPU *cpu)
{
/* Register all the coprocessor registers based on feature bits */
@@ -324,6 +340,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
} else {
define_arm_cp_regs(env, not_v6_cp_reginfo);
}
+ if (arm_feature(env, ARM_FEATURE_V6K)) {
+ define_arm_cp_regs(env, v6k_cp_reginfo);
+ }
if (arm_feature(env, ARM_FEATURE_V7)) {
define_arm_cp_regs(env, v7_cp_reginfo);
} else {
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 660a9d0dc4..c6b91f9499 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2459,64 +2459,9 @@ static int cp15_user_ok(CPUARMState *env, uint32_t insn)
}
return 0;
}
-
- if (cpn == 13 && cpm == 0) {
- /* TLS register. */
- if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
- return 1;
- }
return 0;
}
-static int cp15_tls_load_store(CPUARMState *env, DisasContext *s, uint32_t insn, uint32_t rd)
-{
- TCGv tmp;
- int cpn = (insn >> 16) & 0xf;
- int cpm = insn & 0xf;
- int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
-
- if (!arm_feature(env, ARM_FEATURE_V6K))
- return 0;
-
- if (!(cpn == 13 && cpm == 0))
- return 0;
-
- if (insn & ARM_CP_RW_BIT) {
- switch (op) {
- case 2:
- tmp = load_cpu_field(cp15.c13_tls1);
- break;
- case 3:
- tmp = load_cpu_field(cp15.c13_tls2);
- break;
- case 4:
- tmp = load_cpu_field(cp15.c13_tls3);
- break;
- default:
- return 0;
- }
- store_reg(s, rd, tmp);
-
- } else {
- tmp = load_reg(s, rd);
- switch (op) {
- case 2:
- store_cpu_field(tmp, cp15.c13_tls1);
- break;
- case 3:
- store_cpu_field(tmp, cp15.c13_tls2);
- break;
- case 4:
- store_cpu_field(tmp, cp15.c13_tls3);
- break;
- default:
- tcg_temp_free_i32(tmp);
- return 0;
- }
- }
- return 1;
-}
-
/* Disassemble system coprocessor (cp15) instruction. Return nonzero if
instruction is not defined. */
static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
@@ -2547,9 +2492,6 @@ static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
rd = (insn >> 12) & 0xf;
- if (cp15_tls_load_store(env, s, insn, rd))
- return 0;
-
tmp2 = tcg_const_i32(insn);
if (insn & ARM_CP_RW_BIT) {
tmp = tcg_temp_new_i32();