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authorPeter Maydell <peter.maydell@linaro.org>2012-03-20 17:25:52 +0000
committerPeter Maydell <peter.maydell@linaro.org>2012-03-23 13:42:23 +0000
commit908bdbdbde5848d27c706e46d9808b54daf11ca8 (patch)
tree8a2f434061e2f40d5283deea8f06b2fa43adceda
parent3a181bd2b8a0f90e1f0bb6fd2d3bf2e81be01535 (diff)
downloadqemu-arm-908bdbdbde5848d27c706e46d9808b54daf11ca8.tar.gz
target-arm: Convert TEECR, TEEHBR to new scheme
Convert the THUMB2EE cp14 registers TEECR and TEEHBR to use arm_cp_reginfo.
-rw-r--r--target-arm/helper.c56
-rw-r--r--target-arm/helper.h2
-rw-r--r--target-arm/translate.c66
3 files changed, 47 insertions, 77 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index a5fbf35020..3c5ec47628 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -209,6 +209,37 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
return 0;
}
+static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ value &= 1;
+ env->teecr = value;
+ return 0;
+}
+
+static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t *value)
+{
+ /* This is a helper function because the user access rights
+ * depend on the value of the TEECR.
+ */
+ if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
+ return EXCP_UDEF;
+ }
+ *value = env->teehbr;
+ return 0;
+}
+
+static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
+ return EXCP_UDEF;
+ }
+ env->teehbr = value;
+ return 0;
+}
+
static const ARMCPRegInfo cp_reginfo[] = {
/* DBGDIDR: just RAZ. In particular this means the "debug architecture
* version" bits will read as a reserved value, which should cause
@@ -230,6 +261,19 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
REGINFO_SENTINEL
};
+static const ARMCPRegInfo t2ee_cp_reginfo[] = {
+ /* TODO this should be doable as a FIELD if we support masks. */
+ { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
+ .resetvalue = 0,
+ .writefn = teecr_write },
+ { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
+ .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
+ .resetvalue = 0,
+ .readfn = teehbr_read, .writefn = teehbr_write },
+ REGINFO_SENTINEL
+};
+
void register_cp_regs_for_features(ARMCPU *cpu)
{
/* Register all the coprocessor registers based on feature bits */
@@ -243,6 +287,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (arm_feature(env, ARM_FEATURE_V7)) {
define_arm_cp_regs(env, v7_cp_reginfo);
}
+ if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
+ define_arm_cp_regs(env, t2ee_cp_reginfo);
+ }
}
CPUARMState *cpu_arm_init(const char *cpu_model)
@@ -3073,12 +3120,3 @@ float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
float_status *fpst = fpstp;
return float64_muladd(a, b, c, 0, fpst);
}
-
-void HELPER(set_teecr)(CPUARMState *env, uint32_t val)
-{
- val &= 1;
- if (env->teecr != val) {
- env->teecr = val;
- tb_flush(env);
- }
-}
diff --git a/target-arm/helper.h b/target-arm/helper.h
index bb6b85da72..a0034ae630 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -461,8 +461,6 @@ DEF_HELPER_3(iwmmxt_muladdsl, i64, i64, i32, i32)
DEF_HELPER_3(iwmmxt_muladdsw, i64, i64, i32, i32)
DEF_HELPER_3(iwmmxt_muladdswl, i64, i64, i32, i32)
-DEF_HELPER_2(set_teecr, void, env, i32)
-
DEF_HELPER_3(neon_unzip8, void, env, i32, i32)
DEF_HELPER_3(neon_unzip16, void, env, i32, i32)
DEF_HELPER_3(neon_qunzip8, void, env, i32, i32)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 273a96ca2a..a01635cddd 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -6354,67 +6354,6 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
return 0;
}
-static int disas_cp14_read(CPUARMState * env, DisasContext *s, uint32_t insn)
-{
- int crn = (insn >> 16) & 0xf;
- int crm = insn & 0xf;
- int op1 = (insn >> 21) & 7;
- int op2 = (insn >> 5) & 7;
- int rt = (insn >> 12) & 0xf;
- TCGv tmp;
-
- if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
- if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
- /* TEECR */
- if (IS_USER(s))
- return 1;
- tmp = load_cpu_field(teecr);
- store_reg(s, rt, tmp);
- return 0;
- }
- if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
- /* TEEHBR */
- if (IS_USER(s) && (env->teecr & 1))
- return 1;
- tmp = load_cpu_field(teehbr);
- store_reg(s, rt, tmp);
- return 0;
- }
- }
- return 1;
-}
-
-static int disas_cp14_write(CPUARMState * env, DisasContext *s, uint32_t insn)
-{
- int crn = (insn >> 16) & 0xf;
- int crm = insn & 0xf;
- int op1 = (insn >> 21) & 7;
- int op2 = (insn >> 5) & 7;
- int rt = (insn >> 12) & 0xf;
- TCGv tmp;
-
- if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
- if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
- /* TEECR */
- if (IS_USER(s))
- return 1;
- tmp = load_reg(s, rt);
- gen_helper_set_teecr(cpu_env, tmp);
- tcg_temp_free_i32(tmp);
- return 0;
- }
- if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
- /* TEEHBR */
- if (IS_USER(s) && (env->teecr & 1))
- return 1;
- tmp = load_reg(s, rt);
- store_cpu_field(tmp, teehbr);
- return 0;
- }
- }
- return 1;
-}
-
static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
{
int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
@@ -6592,11 +6531,6 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
* to ARMCPRegInfo.
*/
switch (cpnum) {
- case 14:
- if (insn & (1 << 20))
- return disas_cp14_read(env, s, insn);
- else
- return disas_cp14_write(env, s, insn);
case 15:
return disas_cp15_insn (env, s, insn);
default: