diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2012-03-23 13:23:11 +0000 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2012-03-23 13:40:47 +0000 |
commit | 8e38aa4c9182f2a793be739193a5d6a60beff13b (patch) | |
tree | 73de035f0aa42eec4693c659712769875d8b9a84 | |
parent | 1e405a746c183b4de33b6232eee15126df311036 (diff) |
target-arm: Move c0_cachetype to ARMCPU
Move c0_cachetype value to ARMCPU and out of cpu_reset_model_id().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r-- | target-arm/cpu-qom.h | 1 | ||||
-rw-r--r-- | target-arm/cpu.c | 23 | ||||
-rw-r--r-- | target-arm/helper.c | 12 |
3 files changed, 24 insertions, 12 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 074a2b7a61..bf2e9d4bb5 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -66,6 +66,7 @@ typedef struct ARMCPU { uint32_t reset_fpsid; uint32_t mvfr0; uint32_t mvfr1; + uint32_t ctr; } ARMCPU; static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index dc1de5395c..cfe4cd6512 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -48,6 +48,7 @@ static void arm_cpu_reset(CPUState *c) env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; + env->cp15.c0_cachetype = cpu->ctr; #if defined(CONFIG_USER_ONLY) env->uncached_cpsr = ARM_CPU_MODE_USR; @@ -171,6 +172,7 @@ static void arm926_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP); cpu->env.cp15.c0_cpuid = 0x41069265; cpu->reset_fpsid = 0x41011090; + cpu->ctr = 0x1dd20d2; arm_cpu_postconfig_init(cpu); } @@ -180,6 +182,7 @@ static void arm946_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_MPU); cpu->env.cp15.c0_cpuid = 0x41059461; + cpu->ctr = 0x0f004006; arm_cpu_postconfig_init(cpu); } @@ -191,6 +194,7 @@ static void arm1026_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_AUXCR); cpu->env.cp15.c0_cpuid = 0x4106a262; cpu->reset_fpsid = 0x410110a0; + cpu->ctr = 0x1dd20d2; arm_cpu_postconfig_init(cpu); } @@ -203,6 +207,7 @@ static void arm1136_r2_initfn(Object *obj) cpu->reset_fpsid = 0x410120b4; cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; + cpu->ctr = 0x1dd20d2; arm_cpu_postconfig_init(cpu); } @@ -216,6 +221,7 @@ static void arm1136_initfn(Object *obj) cpu->reset_fpsid = 0x410120b4; cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; + cpu->ctr = 0x1dd20d2; arm_cpu_postconfig_init(cpu); } @@ -229,6 +235,7 @@ static void arm1176_initfn(Object *obj) cpu->reset_fpsid = 0x410120b5; cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; + cpu->ctr = 0x1dd20d2; arm_cpu_postconfig_init(cpu); } @@ -242,6 +249,7 @@ static void arm11mpcore_initfn(Object *obj) cpu->reset_fpsid = 0x410120b4; cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; + cpu->ctr = 0x1dd20d2; arm_cpu_postconfig_init(cpu); } @@ -265,6 +273,7 @@ static void cortex_a8_initfn(Object *obj) cpu->reset_fpsid = 0x410330c0; cpu->mvfr0 = 0x11110222; cpu->mvfr1 = 0x00011100; + cpu->ctr = 0x82048004; arm_cpu_postconfig_init(cpu); } @@ -285,6 +294,7 @@ static void cortex_a9_initfn(Object *obj) cpu->reset_fpsid = 0x41033090; cpu->mvfr0 = 0x11110222; cpu->mvfr1 = 0x01111111; + cpu->ctr = 0x80038003; arm_cpu_postconfig_init(cpu); } @@ -303,6 +313,7 @@ static void cortex_a15_initfn(Object *obj) cpu->reset_fpsid = 0x410430f0; cpu->mvfr0 = 0x10110222; cpu->mvfr1 = 0x11111111; + cpu->ctr = 0x8444c004; arm_cpu_postconfig_init(cpu); } @@ -312,6 +323,7 @@ static void ti925t_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V4T); set_feature(&cpu->env, ARM_FEATURE_OMAPCP); cpu->env.cp15.c0_cpuid = 0x41069265; + cpu->ctr = 0x5109149; arm_cpu_postconfig_init(cpu); } @@ -337,6 +349,7 @@ static void pxa250_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->env.cp15.c0_cpuid = 0x69052100; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -346,6 +359,7 @@ static void pxa255_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->env.cp15.c0_cpuid = 0x69052d00; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -355,6 +369,7 @@ static void pxa260_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->env.cp15.c0_cpuid = 0x69052903; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -364,6 +379,7 @@ static void pxa261_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->env.cp15.c0_cpuid = 0x69052d05; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -373,6 +389,7 @@ static void pxa262_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->env.cp15.c0_cpuid = 0x69052d06; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -383,6 +400,7 @@ static void pxa270a0_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->env.cp15.c0_cpuid = 0x69054110; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -393,6 +411,7 @@ static void pxa270a1_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->env.cp15.c0_cpuid = 0x69054111; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -403,6 +422,7 @@ static void pxa270b0_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->env.cp15.c0_cpuid = 0x69054112; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -413,6 +433,7 @@ static void pxa270b1_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->env.cp15.c0_cpuid = 0x69054113; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -423,6 +444,7 @@ static void pxa270c0_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->env.cp15.c0_cpuid = 0x69054114; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } @@ -437,6 +459,7 @@ static void pxa270c5_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); set_feature(&cpu->env, ARM_FEATURE_V7MP); cpu->env.cp15.c0_cpuid = 0x69054117; + cpu->ctr = 0xd172172; arm_cpu_postconfig_init(cpu); } diff --git a/target-arm/helper.c b/target-arm/helper.c index 0883e51904..02996e13ba 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -48,15 +48,12 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) { switch (id) { case ARM_CPUID_ARM926: - env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00090078; break; case ARM_CPUID_ARM946: - env->cp15.c0_cachetype = 0x0f004006; env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_ARM1026: - env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00090078; break; case ARM_CPUID_ARM1136: @@ -72,24 +69,20 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) */ memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM1176: memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM11MPCORE: memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c0_cachetype = 0x1dd20d2; break; case ARM_CPUID_CORTEXA8: memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c0_cachetype = 0x82048004; env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3; env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */ env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */ @@ -99,7 +92,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_CORTEXA9: memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c0_cachetype = 0x80038003; env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3; env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */ env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */ @@ -108,7 +100,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_CORTEXA15: memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, cortexa15_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c0_cachetype = 0x8444c004; env->cp15.c0_clid = 0x0a200023; env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */ env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */ @@ -122,7 +113,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_TI915T: case ARM_CPUID_TI925T: env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */ - env->cp15.c0_cachetype = 0x5109149; env->cp15.c1_sys = 0x00000070; env->cp15.c15_i_max = 0x000; env->cp15.c15_i_min = 0xff0; @@ -133,7 +123,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA261: case ARM_CPUID_PXA262: /* JTAG_ID is ((id << 28) | 0x09265013) */ - env->cp15.c0_cachetype = 0xd172172; env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_PXA270_A0: @@ -144,7 +133,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA270_C5: /* JTAG_ID is ((id << 28) | 0x09265013) */ env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; - env->cp15.c0_cachetype = 0xd172172; env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_SA1100: |