aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorPeter Maydell <peter.maydell@linaro.org>2012-03-20 17:25:55 +0000
committerPeter Maydell <peter.maydell@linaro.org>2012-03-23 13:42:50 +0000
commit89f1cab3012a83825db84fadd7c5c579d1fc6f58 (patch)
tree1f11a098edfa0b65708e2cf3685a2542e1f1b7e1
parent4ad5fbf5e1f72310722606b1bd5ef75625cbb950 (diff)
downloadqemu-arm-89f1cab3012a83825db84fadd7c5c579d1fc6f58.tar.gz
target-arm: Convert cp15 crn=13 registers
Convert the cp15 crn=13 registers (FCSEIDR, CONTEXTIDR, and the ARM946 Trace Process Identifier Register). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/helper.c61
1 files changed, 31 insertions, 30 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f33e977dba..1fbfb385cc 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -365,6 +365,31 @@ static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
return 0;
}
+static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
+{
+ if (env->cp15.c13_fcse != value) {
+ /* Unlike real hardware the qemu TLB uses virtual addresses,
+ * not modified virtual addresses, so this causes a TLB flush.
+ */
+ tlb_flush(env, 1);
+ env->cp15.c13_fcse = value;
+ }
+ return 0;
+}
+static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
+ /* For VMSA (when not using the LPAE long descriptor page table
+ * format) this register includes the ASID, so do a TLB flush.
+ * For PMSA it is purely a process ID and no action is needed.
+ */
+ tlb_flush(env, 1);
+ }
+ env->cp15.c13_context = value;
+ return 0;
+}
+
static const ARMCPRegInfo cp_reginfo[] = {
/* DBGDIDR: just RAZ. In particular this means the "debug architecture
* version" bits will read as a reserved value, which should cause
@@ -377,6 +402,12 @@ static const ARMCPRegInfo cp_reginfo[] = {
.crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
.resetvalue = 0, .writefn = dacr_write },
+ { .name = "FCSEIDR", .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
+ .resetvalue = 0, .writefn = fcse_write },
+ { .name = "CONTEXTIDR", .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
+ .resetvalue = 0, .writefn = contextidr_write },
REGINFO_SENTINEL
};
@@ -1907,27 +1938,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
break;
case 12: /* Reserved. */
goto bad_reg;
- case 13: /* Process ID. */
- switch (op2) {
- case 0:
- /* Unlike real hardware the qemu TLB uses virtual addresses,
- not modified virtual addresses, so this causes a TLB flush.
- */
- if (env->cp15.c13_fcse != val)
- tlb_flush(env, 1);
- env->cp15.c13_fcse = val;
- break;
- case 1:
- /* This changes the ASID, so do a TLB flush. */
- if (env->cp15.c13_context != val
- && !arm_feature(env, ARM_FEATURE_MPU))
- tlb_flush(env, 0);
- env->cp15.c13_context = val;
- break;
- default:
- goto bad_reg;
- }
- break;
case 15: /* Implementation specific. */
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
if (op2 == 0 && crm == 1) {
@@ -2209,15 +2219,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
case 11: /* TCM DMA control. */
case 12: /* Reserved. */
goto bad_reg;
- case 13: /* Process ID. */
- switch (op2) {
- case 0:
- return env->cp15.c13_fcse;
- case 1:
- return env->cp15.c13_context;
- default:
- goto bad_reg;
- }
case 15: /* Implementation specific. */
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
if (op2 == 0 && crm == 1)