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authorPeter Maydell <peter.maydell@linaro.org>2012-03-20 17:25:52 +0000
committerPeter Maydell <peter.maydell@linaro.org>2012-03-23 13:42:20 +0000
commit3a181bd2b8a0f90e1f0bb6fd2d3bf2e81be01535 (patch)
tree20b64ad88a14f0e5df3c4bb7286a59d3b78d21c2
parentcb940ee9c674e5289cebf012468cc9a7235d229c (diff)
downloadqemu-arm-3a181bd2b8a0f90e1f0bb6fd2d3bf2e81be01535.tar.gz
target-arm: Convert debug registers to cp_reginfo
Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to the cp_reginfo scheme.
-rw-r--r--target-arm/helper.c25
-rw-r--r--target-arm/translate.c28
2 files changed, 25 insertions, 28 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index b241cb7a24..a5fbf35020 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -209,6 +209,27 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
return 0;
}
+static const ARMCPRegInfo cp_reginfo[] = {
+ /* DBGDIDR: just RAZ. In particular this means the "debug architecture
+ * version" bits will read as a reserved value, which should cause
+ * Linux to not try to use the debug hardware.
+ */
+ { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
+ .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ REGINFO_SENTINEL
+};
+
+static const ARMCPRegInfo v7_cp_reginfo[] = {
+ /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
+ * debug components
+ */
+ { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
+ .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "DBGDRAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
+ .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ REGINFO_SENTINEL
+};
+
void register_cp_regs_for_features(ARMCPU *cpu)
{
/* Register all the coprocessor registers based on feature bits */
@@ -218,6 +239,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
return;
}
+ define_arm_cp_regs(env, cp_reginfo);
+ if (arm_feature(env, ARM_FEATURE_V7)) {
+ define_arm_cp_regs(env, v7_cp_reginfo);
+ }
}
CPUARMState *cpu_arm_init(const char *cpu_model)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index ee71ad79e7..273a96ca2a 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -6363,34 +6363,6 @@ static int disas_cp14_read(CPUARMState * env, DisasContext *s, uint32_t insn)
int rt = (insn >> 12) & 0xf;
TCGv tmp;
- /* Minimal set of debug registers, since we don't support debug */
- if (op1 == 0 && crn == 0 && op2 == 0) {
- switch (crm) {
- case 0:
- /* DBGDIDR: just RAZ. In particular this means the
- * "debug architecture version" bits will read as
- * a reserved value, which should cause Linux to
- * not try to use the debug hardware.
- */
- tmp = tcg_const_i32(0);
- store_reg(s, rt, tmp);
- return 0;
- case 1:
- case 2:
- /* DBGDRAR and DBGDSAR: v7 only. Always RAZ since we
- * don't implement memory mapped debug components
- */
- if (ENABLE_ARCH_7) {
- tmp = tcg_const_i32(0);
- store_reg(s, rt, tmp);
- return 0;
- }
- break;
- default:
- break;
- }
- }
-
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
/* TEECR */