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authorPeter Maydell <peter.maydell@linaro.org>2012-03-20 17:25:54 +0000
committerPeter Maydell <peter.maydell@linaro.org>2012-03-23 13:42:43 +0000
commit340a785df787808ab680af26999d754102ddda22 (patch)
tree87aa1f750f24a086e19661572cc92fc630554bf0
parent4fa1dd2cb880159dfdac2b82d2543ea1ecea2b7b (diff)
downloadqemu-arm-340a785df787808ab680af26999d754102ddda22.tar.gz
target-arm: Convert cp15 c3 register
Convert the cp15 c3 register (MMU domain access control or MPU write buffer control). NB that this is horribly underdecoded for modern cores (should be crn=3,crm=0, opc1=0,opc2=0) but this change preserves the existing QEMU behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/helper.c18
1 files changed, 12 insertions, 6 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e660f9bde6..175304e5b4 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -358,6 +358,13 @@ static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
return 0;
}
+static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
+{
+ env->cp15.c3 = value;
+ tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
+ return 0;
+}
+
static const ARMCPRegInfo cp_reginfo[] = {
/* DBGDIDR: just RAZ. In particular this means the "debug architecture
* version" bits will read as a reserved value, which should cause
@@ -365,6 +372,11 @@ static const ARMCPRegInfo cp_reginfo[] = {
*/
{ .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ /* MMU Domain access control / MPU write buffer control */
+ { .name = "DACR", .cp = 15,
+ .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
+ .resetvalue = 0, .writefn = dacr_write },
REGINFO_SENTINEL
};
@@ -1695,10 +1707,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
}
}
break;
- case 3: /* MMU Domain access control / MPU write buffer control. */
- env->cp15.c3 = val;
- tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
- break;
case 4: /* Reserved. */
goto bad_reg;
case 5: /* MMU Fault status / MPU access permission. */
@@ -2086,8 +2094,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
goto bad_reg;
}
}
- case 3: /* MMU Domain access control / MPU write buffer control. */
- return env->cp15.c3;
case 4: /* Reserved. */
goto bad_reg;
case 5: /* MMU Fault status / MPU access permission. */