aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorPeter Maydell <peter.maydell@linaro.org>2012-03-23 13:16:25 +0000
committerPeter Maydell <peter.maydell@linaro.org>2012-03-23 13:40:44 +0000
commit1e405a746c183b4de33b6232eee15126df311036 (patch)
tree5309bba13270eb1b8a547b62c09721f6cafce086
parent2e8b35c09c2635d57279eed192c1ee96dde3e1f3 (diff)
downloadqemu-arm-1e405a746c183b4de33b6232eee15126df311036.tar.gz
target-arm: Move MVFR* VFP feature register values to ARMCPU
Move the MVFR* VFP feature register values to ARMCPU, so they are set up by the implementation-specific instance init functions rather than in cpu_reset_model_id(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/cpu-qom.h2
-rw-r--r--target-arm/cpu.c16
-rw-r--r--target-arm/helper.c12
3 files changed, 18 insertions, 12 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 1db71d865a..074a2b7a61 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -64,6 +64,8 @@ typedef struct ARMCPU {
* some of these might become properties eventually.
*/
uint32_t reset_fpsid;
+ uint32_t mvfr0;
+ uint32_t mvfr1;
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index bd3aeb107c..dc1de5395c 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -46,6 +46,8 @@ static void arm_cpu_reset(CPUState *c)
env->cp15.c15_config_base_address = tmp;
env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
+ env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
+ env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
#if defined(CONFIG_USER_ONLY)
env->uncached_cpsr = ARM_CPU_MODE_USR;
@@ -199,6 +201,8 @@ static void arm1136_r2_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->env.cp15.c0_cpuid = 0x4107b362;
cpu->reset_fpsid = 0x410120b4;
+ cpu->mvfr0 = 0x11111111;
+ cpu->mvfr1 = 0x00000000;
arm_cpu_postconfig_init(cpu);
}
@@ -210,6 +214,8 @@ static void arm1136_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->env.cp15.c0_cpuid = 0x4117b363;
cpu->reset_fpsid = 0x410120b4;
+ cpu->mvfr0 = 0x11111111;
+ cpu->mvfr1 = 0x00000000;
arm_cpu_postconfig_init(cpu);
}
@@ -221,6 +227,8 @@ static void arm1176_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VAPA);
cpu->env.cp15.c0_cpuid = 0x410fb767;
cpu->reset_fpsid = 0x410120b5;
+ cpu->mvfr0 = 0x11111111;
+ cpu->mvfr1 = 0x00000000;
arm_cpu_postconfig_init(cpu);
}
@@ -232,6 +240,8 @@ static void arm11mpcore_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VAPA);
cpu->env.cp15.c0_cpuid = 0x410fb022;
cpu->reset_fpsid = 0x410120b4;
+ cpu->mvfr0 = 0x11111111;
+ cpu->mvfr1 = 0x00000000;
arm_cpu_postconfig_init(cpu);
}
@@ -253,6 +263,8 @@ static void cortex_a8_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
cpu->env.cp15.c0_cpuid = 0x410fc080;
cpu->reset_fpsid = 0x410330c0;
+ cpu->mvfr0 = 0x11110222;
+ cpu->mvfr1 = 0x00011100;
arm_cpu_postconfig_init(cpu);
}
@@ -271,6 +283,8 @@ static void cortex_a9_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V7MP);
cpu->env.cp15.c0_cpuid = 0x410fc090;
cpu->reset_fpsid = 0x41033090;
+ cpu->mvfr0 = 0x11110222;
+ cpu->mvfr1 = 0x01111111;
arm_cpu_postconfig_init(cpu);
}
@@ -287,6 +301,8 @@ static void cortex_a15_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
cpu->env.cp15.c0_cpuid = 0x412fc0f1;
cpu->reset_fpsid = 0x410430f0;
+ cpu->mvfr0 = 0x10110222;
+ cpu->mvfr1 = 0x11111111;
arm_cpu_postconfig_init(cpu);
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f79921a6c3..0883e51904 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -70,31 +70,23 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
* for 1136_r2 (in particular r0p2 does not actually implement most
* of the ID registers).
*/
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM1176:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM11MPCORE:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x1dd20d2;
break;
case ARM_CPUID_CORTEXA8:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x82048004;
@@ -105,8 +97,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA9:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x80038003;
@@ -116,8 +106,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA15:
- env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
- env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, cortexa15_cp15_c0_c2, 8 * sizeof(uint32_t));
env->cp15.c0_cachetype = 0x8444c004;