diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2012-03-23 15:00:50 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-03-23 15:00:50 +0000 |
| commit | c28e73030676ed58f86a0ca915be7c7ba049664b (patch) | |
| tree | 1c840212c6999cf4b37e3fd69bdd9f72f91dad99 | |
| parent | 24cb66def2d81d3501f83cdcbf377608f2fd41c6 (diff) | |
target-arm: Move iWMMXT wCID reset to arm_cpu_reset
Move the iWMMXT wCID reset to arm_cpu_reset(). Since
we use the same value for all CPUs with this feature
(with the major/minor revision fields set to the QEMU
specific 'Q' value) there's no need to create an ARMCPU
field just for this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target-arm/cpu.c | 4 | ||||
| -rw-r--r-- | target-arm/helper.c | 1 |
2 files changed, 4 insertions, 1 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 64329257ff..46f76b27a3 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -51,6 +51,10 @@ static void arm_cpu_reset(CPUState *c) env->cp15.c0_cachetype = cpu->ctr; env->cp15.c1_sys = cpu->reset_sctlr; + if (arm_feature(env, ARM_FEATURE_IWMMXT)) { + env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; + } + #if defined(CONFIG_USER_ONLY) env->uncached_cpsr = ARM_CPU_MODE_USR; /* For user mode we must enable access to coprocessors */ diff --git a/target-arm/helper.c b/target-arm/helper.c index e3ce2a69cc..8d703da025 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -120,7 +120,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA270_B1: case ARM_CPUID_PXA270_C0: case ARM_CPUID_PXA270_C5: - env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; break; case ARM_CPUID_SA1100: case ARM_CPUID_SA1110: |