diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2012-03-23 14:13:41 +0000 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2012-03-23 14:13:41 +0000 |
commit | b5417139f466fad83daca9d5804859c4bee7b4aa (patch) | |
tree | f99947f2f1dc8a22d23fc94b0e2f5043e61700c5 | |
parent | 8e38aa4c9182f2a793be739193a5d6a60beff13b (diff) |
target-arm: Move SCTLR reset values to ARMCPU
Move the reset value of SCTLR to ARMCPU and out of
cpu_reset_model_id().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r-- | target-arm/cpu-qom.h | 1 | ||||
-rw-r--r-- | target-arm/cpu.c | 24 | ||||
-rw-r--r-- | target-arm/helper.c | 12 |
3 files changed, 25 insertions, 12 deletions
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index bf2e9d4bb5..9c0db85d4b 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -67,6 +67,7 @@ typedef struct ARMCPU { uint32_t mvfr0; uint32_t mvfr1; uint32_t ctr; + uint32_t reset_sctlr; } ARMCPU; static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index cfe4cd6512..64329257ff 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -49,6 +49,7 @@ static void arm_cpu_reset(CPUState *c) env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; env->cp15.c0_cachetype = cpu->ctr; + env->cp15.c1_sys = cpu->reset_sctlr; #if defined(CONFIG_USER_ONLY) env->uncached_cpsr = ARM_CPU_MODE_USR; @@ -173,6 +174,7 @@ static void arm926_initfn(Object *obj) cpu->env.cp15.c0_cpuid = 0x41069265; cpu->reset_fpsid = 0x41011090; cpu->ctr = 0x1dd20d2; + cpu->reset_sctlr = 0x00090078; arm_cpu_postconfig_init(cpu); } @@ -183,6 +185,7 @@ static void arm946_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_MPU); cpu->env.cp15.c0_cpuid = 0x41059461; cpu->ctr = 0x0f004006; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -195,6 +198,7 @@ static void arm1026_initfn(Object *obj) cpu->env.cp15.c0_cpuid = 0x4106a262; cpu->reset_fpsid = 0x410110a0; cpu->ctr = 0x1dd20d2; + cpu->reset_sctlr = 0x00090078; arm_cpu_postconfig_init(cpu); } @@ -208,6 +212,7 @@ static void arm1136_r2_initfn(Object *obj) cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; cpu->ctr = 0x1dd20d2; + cpu->reset_sctlr = 0x00050078; arm_cpu_postconfig_init(cpu); } @@ -222,6 +227,7 @@ static void arm1136_initfn(Object *obj) cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; cpu->ctr = 0x1dd20d2; + cpu->reset_sctlr = 0x00050078; arm_cpu_postconfig_init(cpu); } @@ -236,6 +242,7 @@ static void arm1176_initfn(Object *obj) cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; cpu->ctr = 0x1dd20d2; + cpu->reset_sctlr = 0x00050078; arm_cpu_postconfig_init(cpu); } @@ -274,6 +281,7 @@ static void cortex_a8_initfn(Object *obj) cpu->mvfr0 = 0x11110222; cpu->mvfr1 = 0x00011100; cpu->ctr = 0x82048004; + cpu->reset_sctlr = 0x00c50078; arm_cpu_postconfig_init(cpu); } @@ -295,6 +303,7 @@ static void cortex_a9_initfn(Object *obj) cpu->mvfr0 = 0x11110222; cpu->mvfr1 = 0x01111111; cpu->ctr = 0x80038003; + cpu->reset_sctlr = 0x00c50078; arm_cpu_postconfig_init(cpu); } @@ -314,6 +323,7 @@ static void cortex_a15_initfn(Object *obj) cpu->mvfr0 = 0x10110222; cpu->mvfr1 = 0x11111111; cpu->ctr = 0x8444c004; + cpu->reset_sctlr = 0x00c50078; arm_cpu_postconfig_init(cpu); } @@ -324,6 +334,7 @@ static void ti925t_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_OMAPCP); cpu->env.cp15.c0_cpuid = 0x41069265; cpu->ctr = 0x5109149; + cpu->reset_sctlr = 0x00000070; arm_cpu_postconfig_init(cpu); } @@ -332,6 +343,7 @@ static void sa1100_initfn(Object *obj) ARMCPU *cpu = ARM_CPU(obj); set_feature(&cpu->env, ARM_FEATURE_STRONGARM); cpu->env.cp15.c0_cpuid = 0x4401A11B; + cpu->reset_sctlr = 0x00000070; arm_cpu_postconfig_init(cpu); } @@ -340,6 +352,7 @@ static void sa1110_initfn(Object *obj) ARMCPU *cpu = ARM_CPU(obj); set_feature(&cpu->env, ARM_FEATURE_STRONGARM); cpu->env.cp15.c0_cpuid = 0x6901B119; + cpu->reset_sctlr = 0x00000070; arm_cpu_postconfig_init(cpu); } @@ -350,6 +363,7 @@ static void pxa250_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->env.cp15.c0_cpuid = 0x69052100; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -360,6 +374,7 @@ static void pxa255_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->env.cp15.c0_cpuid = 0x69052d00; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -370,6 +385,7 @@ static void pxa260_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->env.cp15.c0_cpuid = 0x69052903; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -380,6 +396,7 @@ static void pxa261_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->env.cp15.c0_cpuid = 0x69052d05; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -390,6 +407,7 @@ static void pxa262_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_XSCALE); cpu->env.cp15.c0_cpuid = 0x69052d06; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -401,6 +419,7 @@ static void pxa270a0_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->env.cp15.c0_cpuid = 0x69054110; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -412,6 +431,7 @@ static void pxa270a1_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->env.cp15.c0_cpuid = 0x69054111; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -423,6 +443,7 @@ static void pxa270b0_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->env.cp15.c0_cpuid = 0x69054112; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -434,6 +455,7 @@ static void pxa270b1_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->env.cp15.c0_cpuid = 0x69054113; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -445,6 +467,7 @@ static void pxa270c0_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_IWMMXT); cpu->env.cp15.c0_cpuid = 0x69054114; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } @@ -460,6 +483,7 @@ static void pxa270c5_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7MP); cpu->env.cp15.c0_cpuid = 0x69054117; cpu->ctr = 0xd172172; + cpu->reset_sctlr = 0x00000078; arm_cpu_postconfig_init(cpu); } diff --git a/target-arm/helper.c b/target-arm/helper.c index 02996e13ba..8948cf34ea 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -48,13 +48,10 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) { switch (id) { case ARM_CPUID_ARM926: - env->cp15.c1_sys = 0x00090078; break; case ARM_CPUID_ARM946: - env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_ARM1026: - env->cp15.c1_sys = 0x00090078; break; case ARM_CPUID_ARM1136: /* This is the 1136 r1, which is a v6K core */ @@ -69,12 +66,10 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) */ memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM1176: memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t)); - env->cp15.c1_sys = 0x00050078; break; case ARM_CPUID_ARM11MPCORE: memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t)); @@ -87,7 +82,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */ env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */ env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */ - env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXA9: memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t)); @@ -95,7 +89,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3; env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */ env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */ - env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXA15: memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t)); @@ -104,7 +97,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */ env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */ env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */ - env->cp15.c1_sys = 0x00c50078; break; case ARM_CPUID_CORTEXM3: break; @@ -113,7 +105,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_TI915T: case ARM_CPUID_TI925T: env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */ - env->cp15.c1_sys = 0x00000070; env->cp15.c15_i_max = 0x000; env->cp15.c15_i_min = 0xff0; break; @@ -123,7 +114,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA261: case ARM_CPUID_PXA262: /* JTAG_ID is ((id << 28) | 0x09265013) */ - env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_PXA270_A0: case ARM_CPUID_PXA270_A1: @@ -133,11 +123,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_PXA270_C5: /* JTAG_ID is ((id << 28) | 0x09265013) */ env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; - env->cp15.c1_sys = 0x00000078; break; case ARM_CPUID_SA1100: case ARM_CPUID_SA1110: - env->cp15.c1_sys = 0x00000070; break; default: cpu_abort(env, "Bad CPU ID: %x\n", id); |