diff options
| author | Paolo Bonzini <pbonzini@redhat.com> | 2021-03-18 09:35:56 -0400 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2021-03-19 08:48:18 -0400 |
| commit | b8184135835068e9579e678f0b54465ee6161d32 (patch) | |
| tree | 92cfeadfc6c3c2339440ba970f139c0dafec56a6 | |
| parent | 6d9abb6de9cc53a508823db0283061824f2f98a2 (diff) | |
target/i386: allow modifying TCG phys-addr-bits
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | target/i386/cpu.c | 23 | ||||
| -rw-r--r-- | target/i386/cpu.h | 1 | ||||
| -rw-r--r-- | target/i386/tcg/excp_helper.c | 7 | ||||
| -rw-r--r-- | target/i386/tcg/helper-tcg.h | 12 |
4 files changed, 16 insertions, 27 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ae9fd9f31d..6b3e9467f1 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6785,21 +6785,14 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) cpu->phys_bits = cpu->host_phys_bits_limit; } } - - if (cpu->phys_bits && - (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || - cpu->phys_bits < 32)) { - error_setg(errp, "phys-bits should be between 32 and %u " - " (but is %u)", - TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); - return; - } - } else { - if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) { - error_setg(errp, "TCG only supports phys-bits=%u", - TCG_PHYS_ADDR_BITS); - return; - } + } + if (cpu->phys_bits && + (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || + cpu->phys_bits < 32)) { + error_setg(errp, "phys-bits should be between 32 and %u " + " (but is %u)", + TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); + return; } /* 0 means it was not explicitly set by the user (or by machine * compat_props or by the host code above). In this case, the default diff --git a/target/i386/cpu.h b/target/i386/cpu.h index b4b136cd0d..570f916878 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -290,7 +290,6 @@ typedef enum X86Seg { #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) #define PG_ADDRESS_MASK 0x000ffffffffff000LL -#define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) #define PG_HI_USER_MASK 0x7ff0000000000000LL #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) #define PG_NX_MASK (1ULL << PG_NX_BIT) diff --git a/target/i386/tcg/excp_helper.c b/target/i386/tcg/excp_helper.c index b7d6259e4a..1e71e44510 100644 --- a/target/i386/tcg/excp_helper.c +++ b/target/i386/tcg/excp_helper.c @@ -142,8 +142,9 @@ void raise_exception_ra(CPUX86State *env, int exception_index, uintptr_t retaddr static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type, int *prot) { - CPUX86State *env = &X86_CPU(cs)->env; - uint64_t rsvd_mask = PG_HI_RSVD_MASK; + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + uint64_t rsvd_mask = PG_ADDRESS_MASK & ~MAKE_64BIT_MASK(0, cpu->phys_bits); uint64_t ptep, pte; uint64_t exit_info_1 = 0; target_ulong pde_addr, pte_addr; @@ -358,7 +359,7 @@ static int handle_mmu_fault(CPUState *cs, vaddr addr, int size, int error_code = 0; int is_dirty, prot, page_size, is_write, is_user; hwaddr paddr; - uint64_t rsvd_mask = PG_HI_RSVD_MASK; + uint64_t rsvd_mask = PG_ADDRESS_MASK & ~MAKE_64BIT_MASK(0, cpu->phys_bits); uint32_t page_offset; target_ulong vaddr; uint32_t pkr; diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index c133c63555..ef60e2e04b 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -25,17 +25,13 @@ /* Maximum instruction code size */ #define TARGET_MAX_INSN_SIZE 16 -/* - * XXX: This value should match the one returned by CPUID - * and in exec.c - */ -# if defined(TARGET_X86_64) +#if defined(TARGET_X86_64) # define TCG_PHYS_ADDR_BITS 40 -# else +#else # define TCG_PHYS_ADDR_BITS 36 -# endif +#endif -#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) +QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_SPACE_BITS); /** * x86_cpu_do_interrupt: |