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authorAlexey Kardashevskiy <aik@ozlabs.ru>2014-03-07 15:37:39 +1100
committerAndreas Färber <afaerber@suse.de>2014-03-20 02:39:33 +0100
commitdf99d30d4e0dd22be5572235a5213de429e00747 (patch)
tree3fc69e551541b123c74624e038eed96f6d996e39
parent5ec83c73e5ece590538878b24dfcb422904533e0 (diff)
downloadqemu-arm-df99d30d4e0dd22be5572235a5213de429e00747.tar.gz
target-ppc: Introduce powerisa-207-server flag
This flag will be used to decide whether to emulate some bits of H_SET_MODE hypercall because some are POWER8-only. While we are here, add 2.05 flag to POWER8 family too. POWER7/7+ already have it. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
-rw-r--r--target-ppc/cpu.h2
-rw-r--r--target-ppc/translate_init.c3
2 files changed, 4 insertions, 1 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 8c181e7245..2719c08323 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1901,6 +1901,8 @@ enum {
PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
/* ISA 2.07 Altivec */
PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
+ /* PowerISA 2.07 Book3s specification */
+ PPC2_ISA207S = 0x0000000000008000ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 5302bdc1b2..7f53c33eaf 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7173,7 +7173,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
- PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207;
+ PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
+ PPC2_ISA205 | PPC2_ISA207S;
pcc->msr_mask = 0x800000000284FF36ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)