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authorPeter Maydell <peter.maydell@linaro.org>2014-03-24 15:59:02 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-03-24 16:34:01 +0000
commitd108609bf9ba160d2e2044ce7d553f691ac96dbd (patch)
treef04b92c7a59fcab6825406e9dc608b2e48ae7308
parent3a87f8b6859e6221b827ab4737779dddb37553ec (diff)
downloadqemu-arm-d108609bf9ba160d2e2044ce7d553f691ac96dbd.tar.gz
target-arm: Fix A64 Neon MLS
The order of operands for the accumulate step in disas_simd_3same_int() was reversed. This only affected the MLS instruction, since all the other accumulating instructions in this category perform an addition rather than a subtraction. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/translate-a64.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 9f0645075e..9175e48797 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -8925,7 +8925,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
genfn = fns[size][is_sub];
read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);
- genfn(tcg_res, tcg_res, tcg_op1);
+ genfn(tcg_res, tcg_op1, tcg_res);
}
write_vec_element_i32(s, tcg_res, rd, pass, MO_32);