diff options
| author | Alexander Graf <agraf@suse.de> | 2013-05-13 22:32:50 -0600 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-05-20 19:13:22 +0100 |
| commit | 3d7afd075880359db0fc8cda831d6c8db1b9f68e (patch) | |
| tree | abb14f507a229aa4c846bc716261d7d8f69b1ce2 | |
| parent | e85f78eaf72862585a99c52f5c5c564ff982911d (diff) | |
| download | qemu-arm-3d7afd075880359db0fc8cda831d6c8db1b9f68e.tar.gz | |
ARM: Export cpu_env
The cpu_env tcg variable will be used by both the AArch32 and AArch64
handling code. Unstaticify it, so that both sides can make use of it.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Message-id: 1368505980-17151-3-git-send-email-john.rigby@linaro.org
| -rw-r--r-- | target-arm/translate.c | 2 | ||||
| -rw-r--r-- | target-arm/translate.h | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 93447db16e..f9174f7495 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -59,7 +59,7 @@ static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE]; #define DISAS_WFI 4 #define DISAS_SWI 5 -static TCGv_ptr cpu_env; +TCGv_ptr cpu_env; /* We reuse the same 64-bit temporaries for efficiency. */ static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; static TCGv_i32 cpu_R[16]; diff --git a/target-arm/translate.h b/target-arm/translate.h index e727bc66fe..8ba14339a9 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -24,4 +24,6 @@ typedef struct DisasContext { int vec_stride; } DisasContext; +extern TCGv_ptr cpu_env; + #endif /* TARGET_ARM_TRANSLATE_H */ |