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authorAlexander Graf <agraf@suse.de>2013-08-09 14:19:00 +0100
committerPeter Maydell <peter.maydell@linaro.org>2013-09-03 19:30:31 +0100
commitd561c15a34db5e71bd42ffe823fe2fff4b5fe6e0 (patch)
tree1bc622155b93046afbf2fc930aa648cd530d83f9
parent13064a4e1b16fdace4a50a4be800e53bfd86c61d (diff)
downloadqemu-arm-d561c15a34db5e71bd42ffe823fe2fff4b5fe6e0.tar.gz
target-arm: Fix target_ulong/uint32_t confusions
Correct a few places that were using uint32_t or a 32 bit only format string to handle something that should be a target_ulong. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> [PMM: split out to separate patch; added gen_goto_tb() and gen_set_pc_im() dest params to list of things to change.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/cpu.h4
-rw-r--r--target-arm/translate.c9
2 files changed, 7 insertions, 6 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index f2abdf37ce..8d1cc475c9 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -823,7 +823,7 @@ static inline bool cpu_has_work(CPUState *cpu)
#include "exec/exec-all.h"
/* Load an instruction and return it in the standard little-endian order */
-static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr,
+static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
bool do_swap)
{
uint32_t insn = cpu_ldl_code(env, addr);
@@ -834,7 +834,7 @@ static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr,
}
/* Ditto, for a halfword (Thumb) instruction */
-static inline uint16_t arm_lduw_code(CPUARMState *env, uint32_t addr,
+static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
bool do_swap)
{
uint16_t insn = cpu_lduw_code(env, addr);
diff --git a/target-arm/translate.c b/target-arm/translate.c
index a6adcc89a4..5a465fcab8 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -904,7 +904,7 @@ DO_GEN_ST(st8)
DO_GEN_ST(st16)
DO_GEN_ST(st32)
-static inline void gen_set_pc_im(uint32_t val)
+static inline void gen_set_pc_im(target_ulong val)
{
tcg_gen_movi_i32(cpu_R[15], val);
}
@@ -3412,7 +3412,7 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
return 0;
}
-static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
+static inline void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
{
TranslationBlock *tb;
@@ -9992,7 +9992,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
uint16_t *gen_opc_end;
int j, lj;
target_ulong pc_start;
- uint32_t next_page_start;
+ target_ulong next_page_start;
int num_insns;
int max_insns;
@@ -10146,7 +10146,8 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
}
if (tcg_check_temp_count()) {
- fprintf(stderr, "TCG temporary leak before %08x\n", dc->pc);
+ fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
+ dc->pc);
}
/* Translation stops when a conditional branch is encountered.