diff options
| author | Claudio Fontana <claudio.fontana@linaro.org> | 2013-11-26 14:36:11 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-11-30 20:37:09 +0000 |
| commit | c2a6fea90ef8547bc6fbaef5204f4ac01f514d31 (patch) | |
| tree | c93f183544e9f39d97a8caa90ada864679575f80 | |
| parent | 46ecb0c8080348d62ca756e28a0684184a5ae4e3 (diff) | |
target-arm: aarch64: add support for 1-src data processing and CLZ
this patch adds support for decoding 1-src data processing insns,
and the first user, C5.6.40 CLZ(count leading zeroes).
Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: adapted to new decoder, simpler path for 64bit form,
reuse 32bit helper for 32bit form]
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
From Alexander Graf <agraf@suse.de> aarch64 series 47/60
| -rw-r--r-- | target-arm/helper-a64.c | 5 | ||||
| -rw-r--r-- | target-arm/helper-a64.h | 1 | ||||
| -rw-r--r-- | target-arm/translate-a64.c | 50 |
3 files changed, 54 insertions, 2 deletions
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index f1db953bcc..1a1b52357d 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -41,3 +41,8 @@ int64_t HELPER(sdiv64)(int64_t num, int64_t den) return LLONG_MIN; return num / den; } + +uint64_t HELPER(clz64)(uint64_t x) +{ + return clz64(x); +} diff --git a/target-arm/helper-a64.h b/target-arm/helper-a64.h index 7a03dc0ebc..8ccd1f3654 100644 --- a/target-arm/helper-a64.h +++ b/target-arm/helper-a64.h @@ -19,3 +19,4 @@ DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64) +DEF_HELPER_FLAGS_1(clz64, TCG_CALL_NO_RWG_SE, i64, i64) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 06b453625b..83765044dd 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1093,10 +1093,56 @@ static void disas_cond_select(DisasContext *s, uint32_t insn) } } -/* Data-processing (1 source) */ +static void handle_clz(DisasContext *s, unsigned int sf, + unsigned int rn, unsigned int rd) +{ + TCGv_i64 tcg_rd, tcg_rn; + tcg_rd = cpu_reg(s, rd); + tcg_rn = cpu_reg(s, rn); + + if (sf) { + gen_helper_clz64(tcg_rd, tcg_rn); + } else { + TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(); + tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn); + gen_helper_clz(tcg_tmp32, tcg_tmp32); + tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); + tcg_temp_free_i32(tcg_tmp32); + } +} + +/* C3.5.7 Data-processing (1 source) */ static void disas_data_proc_1src(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + /* + * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0 + * sf 1 S 1 1 0 1 0 1 1 0 opcode2 opcode Rn Rd + * [0] [0 0 0 0 0] + */ + unsigned int sf, opcode, rn, rd; + if (extract32(insn, 16, 15) != 0x5ac0) { + unallocated_encoding(s); + return; + } + sf = insn & (1 << 31) ? 1 : 0; + opcode = extract32(insn, 10, 6); + rn = extract32(insn, 5, 5); + rd = extract32(insn, 0, 5); + + switch (opcode) { + case 0: /* RBIT */ + case 1: /* REV16 */ + case 2: /* REV32 */ + case 3: /* REV64 */ + unsupported_encoding(s, insn); + break; + case 4: /* CLZ */ + handle_clz(s, sf, rn, rd); + break; + case 5: /* CLS */ + unsupported_encoding(s, insn); + break; + } } static void handle_div(DisasContext *s, bool is_signed, unsigned int sf, |