diff options
author | Claudio Fontana <claudio.fontana@linaro.org> | 2013-11-26 18:15:55 +0100 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2013-11-30 20:37:09 +0000 |
commit | a969878ba5f327694dfdefae6949eea6ea683994 (patch) | |
tree | 837f324ef73da1f7638deb120207188292a67602 | |
parent | 6cc21efb2de24693bc1d5a9823beccecd7bae1ed (diff) |
target-arm: aarch64: add support for 1-src REV insns
this adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
From Alexander Graf <agraf@suse.de> aarch64 series 46/60
-rw-r--r-- | target-arm/translate-a64.c | 74 |
1 files changed, 73 insertions, 1 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 0481241519..79a9f8e359 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1129,6 +1129,74 @@ static void handle_rbit(DisasContext *s, unsigned int sf, } } +/* C5.6.149 REV with sf==1, opcode==3 ("REV64") */ +static void handle_rev64(DisasContext *s, unsigned int sf, + unsigned int rn, unsigned int rd) +{ + if (!sf) { + unallocated_encoding(s); + return; + } + tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn)); +} + +/* C5.6.149 REV with sf==0, opcode==2 */ +/* C5.6.151 REV32 (sf==1, opcode==2) */ +static void handle_rev32(DisasContext *s, unsigned int sf, + unsigned int rn, unsigned int rd) +{ + TCGv_i64 tcg_rd, tcg_rn; + tcg_rd = cpu_reg(s, rd); + tcg_rn = cpu_reg(s, rn); + + if (sf) { + TCGv_i64 tcg_tmp = tcg_temp_new_i64(); + tcg_gen_andi_i64(tcg_tmp, tcg_rn, 0xffffffff); + tcg_gen_bswap32_i64(tcg_rd, tcg_tmp); + tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32); + tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp); + tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 32, 32); + tcg_temp_free_i64(tcg_tmp); + } else { + tcg_gen_ext32u_i64(tcg_rd, tcg_rn); + tcg_gen_bswap32_i64(tcg_rd, tcg_rd); + } +} + +/* C5.6.150 REV16 (opcode==1) */ +static void handle_rev16(DisasContext *s, unsigned int sf, + unsigned int rn, unsigned int rd) +{ + TCGv_i64 tcg_rd, tcg_rn, tcg_tmp; + tcg_rd = cpu_reg(s, rd); + tcg_rn = cpu_reg(s, rn); + + tcg_tmp = tcg_temp_new_i64(); + tcg_gen_andi_i64(tcg_tmp, tcg_rn, 0xffff); + tcg_gen_bswap16_i64(tcg_rd, tcg_tmp); + + tcg_gen_shri_i64(tcg_tmp, tcg_rn, 16); + tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff); + tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); + tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 16, 16); + + if (!sf) { /* done */ + tcg_temp_free_i64(tcg_tmp); + return; + } + + tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32); + tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff); + tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); + tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 32, 16); + + tcg_gen_shri_i64(tcg_tmp, tcg_rn, 48); + tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp); + tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 48, 16); + + tcg_temp_free_i64(tcg_tmp); +} + /* C3.5.7 Data-processing (1 source) */ static void disas_data_proc_1src(DisasContext *s, uint32_t insn) { @@ -1152,9 +1220,13 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn) handle_rbit(s, sf, rn, rd); break; case 1: /* REV16 */ + handle_rev16(s, sf, rn, rd); + break; case 2: /* REV32 */ + handle_rev32(s, sf, rn, rd); + break; case 3: /* REV64 */ - unsupported_encoding(s, insn); + handle_rev64(s, sf, rn, rd); break; case 4: /* CLZ */ handle_clz(s, sf, rn, rd); |