diff options
| author | Alex Bennée <alex@bennee.com> | 2013-11-25 14:34:40 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-11-30 20:37:09 +0000 |
| commit | 9da1a7aefb34ea9af1028d3d7d04619182fbef6a (patch) | |
| tree | f55af88be439c0fbc414d821b0b31e3b94cc505c | |
| parent | 057a4d2c83fea467f04b5a26d41cf976e43ee437 (diff) | |
target-arm: aarch64: add support for ld lit
Adds support for Load Register (literal).
from Alexander Graf <agraf@suse.de> aarch64 series 40/60
| -rw-r--r-- | target-arm/translate-a64.c | 51 |
1 files changed, 47 insertions, 4 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index cb4bb12e8e..718bfcc950 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -954,10 +954,53 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) unsupported_encoding(s, insn); } -/* Load register (literal) */ -static void disas_ld_lit(DisasContext *s, uint32_t insn) +/* C3.3.5 Load register (literal) + + 31 30 29 27 26 25 24 23 5 4 0 + +-----+-------+--+-----+-------------------+-------+ + | opc | 0 1 1 |V | 0 0 | imm19 | Rt | + +-----+-------+--+-----+-------------------+-------+ + + opc: 00 -> 32bit, 01 -> 64bit, 10-> 64bit signed, 11 -> prefetch + V: 1 -> vector (simd/fp) + */ +static void handle_ld_lit(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + int rt = extract32(insn, 0, 5); + int64_t imm = sextract32(insn, 5, 19) << 2; + bool is_vector = extract32(insn, 26, 1); + int opc = extract32(insn, 30, 2); + + TCGv_i64 tcg_rt = cpu_reg(s, rt); + TCGv_i64 tcg_addr; + bool is_signed = false; + int size = 2; + + switch (opc) { + case 0: + is_signed = false; + size = 2; + break; + case 1: + is_signed = false; + size = 3; + break; + case 2: + is_signed = true; + size = 2; + break; + case 3: + /* prefetch */ + return; + } + + if (is_vector) { + unsupported_encoding(s, insn); + } else { + tcg_addr = tcg_const_i64((s->pc - 4) + imm); + do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed); + tcg_temp_free_i64(tcg_addr); + } } /* @@ -1165,7 +1208,7 @@ static void disas_ldst(DisasContext *s, uint32_t insn) disas_ldst_excl(s, insn); break; case 0x18: case 0x1c: /* Load register (literal) */ - disas_ld_lit(s, insn); + handle_ld_lit(s, insn); break; case 0x28: case 0x29: case 0x2c: case 0x2d: /* Load/store pair (all forms) */ |