diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2014-02-11 18:41:33 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-14 15:35:10 +0000 |
| commit | eb0b7452e769e5b41e4ceae1c654ee5654574bcf (patch) | |
| tree | 64967d5ee344895d502067dab8014fac079437b8 | |
| parent | 0a180606f48752c0643d02d5c5ac37efe9703f19 (diff) | |
target-arm: Implement AArch64 DAIF system register
Implement the DAIF system register which is a view of the
DAIF bits in PSTATE.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
| -rw-r--r-- | target-arm/helper.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index 367fbbeb0d..c50ca5a98a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1589,6 +1589,25 @@ static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, vfp_set_fpsr(env, value); } +static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri) +{ + if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + +static uint64_t aa64_daif_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->daif; +} + +static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->daif = value & PSTATE_DAIF; +} + static CPAccessResult aa64_cacheop_access(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -1632,6 +1651,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { { .name = "NZCV", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, .access = PL0_RW, .type = ARM_CP_NZCV }, + { .name = "DAIF", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, + .type = ARM_CP_NO_MIGRATE, + .access = PL0_RW, .accessfn = aa64_daif_access, + .readfn = aa64_daif_read, .writefn = aa64_daif_write }, { .name = "FPCR", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, |