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authorPeter Maydell <peter.maydell@linaro.org>2014-04-24 16:24:23 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-04-24 16:51:11 +0100
commit77c017ef332b93cdff8ba7f8edcfccacacba6bc2 (patch)
treef552450501a0b679ca1f1e068a1ae612bc191582
parent3fde545654d4fc451c8d57c870abfc663256b66e (diff)
downloadqemu-arm-77c017ef332b93cdff8ba7f8edcfccacacba6bc2.tar.gz
hw/arm/virt: Put GIC register banks on 64K boundaries
For an AArch64 CPU which supports 64K pages, having the GIC register banks at 4K offsets is potentially awkward. Move them out to being at 64K offsets. (This is harmless for AArch32 CPUs and for AArch64 CPUs with 4K pages, so it is simpler to use the same offsets everywhere than to try to use 64K offsets only for AArch64 host CPUs.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/arm/virt.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index ecff256dac..9c4d337b1b 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -96,10 +96,10 @@ typedef struct VirtBoardInfo {
static const MemMapEntry a15memmap[] = {
/* Space up to 0x8000000 is reserved for a boot ROM */
[VIRT_FLASH] = { 0, 0x8000000 },
- [VIRT_CPUPERIPHS] = { 0x8000000, 0x8000 },
+ [VIRT_CPUPERIPHS] = { 0x8000000, 0x20000 },
/* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
- [VIRT_GIC_DIST] = { 0x8001000, 0x1000 },
- [VIRT_GIC_CPU] = { 0x8002000, 0x1000 },
+ [VIRT_GIC_DIST] = { 0x8000000, 0x10000 },
+ [VIRT_GIC_CPU] = { 0x8010000, 0x10000 },
[VIRT_UART] = { 0x9000000, 0x1000 },
[VIRT_MMIO] = { 0xa000000, 0x200 },
/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */