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authorWill Newton <will.newton@linaro.org>2013-12-05 12:11:11 +0000
committerPeter Maydell <peter.maydell@linaro.org>2013-12-31 13:04:29 +0000
commita9013d91f8be11d1fbf4972f61139c3ff0b0d2ad (patch)
tree1e13b81864735e8d9b84e16096d6f1f2a066ae09
parent9c1d83337479c770deea547643f9a7f1a8470fb9 (diff)
downloadqemu-arm-a9013d91f8be11d1fbf4972f61139c3ff0b0d2ad.tar.gz
target-arm: A64: Add floating-point<->integer conversion instructions
Add support for the AArch64 floating-point <-> integer conversion instructions to disas_fpintconv. In the process we can rearrange and simplify the detection of unallocated encodings a little. We also correct a typo in the instruction encoding diagram for this instruction group: bit 21 is 1, not 0. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/translate-a64.c23
1 files changed, 20 insertions, 3 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index ec8abc708a..9b23d37483 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -3904,7 +3904,7 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
/* C3.6.30 Floating point <-> integer conversions
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
* +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
- * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
+ * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
* +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
*/
static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
@@ -3917,10 +3917,20 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
bool sbit = extract32(insn, 29, 1);
bool sf = extract32(insn, 31, 1);
- if (!sbit && (rmode < 2) && (opcode > 5)) {
+ if (sbit) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ if (opcode > 5) {
/* FMOV */
bool itof = opcode & 1;
+ if (rmode >= 2) {
+ unallocated_encoding(s);
+ return;
+ }
+
switch (sf << 3 | type << 1 | rmode) {
case 0x0: /* 32 bit */
case 0xa: /* 64 bit */
@@ -3935,7 +3945,14 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
handle_fmov(s, rd, rn, type, itof);
} else {
/* actual FP conversions */
- unsupported_encoding(s, insn);
+ bool itof = extract32(opcode, 1, 1);
+
+ if (type > 1 || (rmode != 0 && opcode > 1)) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type);
}
}