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authorAlexander Graf <agraf@suse.de>2013-12-02 14:37:14 +0000
committerPeter Maydell <peter.maydell@linaro.org>2013-12-23 23:28:24 +0000
commit3867227b1149b1a757197f94aee78e9a926d0526 (patch)
tree77d338ba7d5ac823ea36ac80fd7147922c872e94
parentf0c23a628e142e6c877ea49b489f9dfc77cbcbfc (diff)
downloadqemu-arm-3867227b1149b1a757197f94aee78e9a926d0526.tar.gz
target-arm: A64: Add support for dumping AArch64 VFP register state
When dumping the current CPU state, we can also get a request to dump the FPU state along with the CPU's integer state. Add support to dump the VFP state when that flag is set, so that we can properly debug code that modifies floating point registers. Signed-off-by: Alexander Graf <agraf@suse.de> [WN: Commit message tweak, rebased. Output all registers, two per-line.] Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
-rw-r--r--target-arm/translate-a64.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 40c6fc4a9b..326f36d589 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -119,6 +119,22 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
psr & PSTATE_C ? 'C' : '-',
psr & PSTATE_V ? 'V' : '-');
cpu_fprintf(f, "\n");
+
+ if (flags & CPU_DUMP_FPU) {
+ int numvfpregs = 32;
+ for (i = 0; i < numvfpregs; i += 2) {
+ uint64_t vlo = float64_val(env->vfp.regs[i * 2]);
+ uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]);
+ cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 " ",
+ i, vhi, vlo);
+ vlo = float64_val(env->vfp.regs[(i + 1) * 2]);
+ vhi = float64_val(env->vfp.regs[((i + 1) * 2) + 1]);
+ cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "\n",
+ i + 1, vhi, vlo);
+ }
+ cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n",
+ vfp_get_fpcr(env), vfp_get_fpsr(env));
+ }
}
static int get_mem_index(DisasContext *s)