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authorAlexander Graf <agraf@suse.de>2013-11-20 11:20:47 +0100
committerPeter Maydell <peter.maydell@linaro.org>2013-12-06 17:24:02 +0000
commite2f21db172fa040a65426613cc3a17affa209b81 (patch)
tree256c3db5d9e6994ba52459bc57944e886fe98026
parent3a8390c61bd048a69ab7cbc92bba4a6a6ca39aed (diff)
downloadqemu-arm-e2f21db172fa040a65426613cc3a17affa209b81.tar.gz
target-arm: A64: add support for ADR and ADRP
Add support for the instructions described in "C3.4.6 PC-rel. addressing" (ADR and ADRP). Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder structure] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
-rw-r--r--target-arm/translate-a64.c25
1 files changed, 23 insertions, 2 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 6d42177ca8..9e11621636 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -653,10 +653,31 @@ static void disas_ldst(DisasContext *s, uint32_t insn)
}
}
-/* PC-rel. addressing */
+/* C3.4.6 PC-rel. addressing
+ * 31 30 29 28 24 23 5 4 0
+ * +----+-------+-----------+-------------------+------+
+ * | op | immlo | 1 0 0 0 0 | immhi | Rd |
+ * +----+-------+-----------+-------------------+------+
+ */
static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
{
- unsupported_encoding(s, insn);
+ unsigned int page, rd;
+ uint64_t base;
+ int64_t offset;
+
+ page = extract32(insn, 31, 1);
+ /* SignExtend(immhi:immlo) -> offset */
+ offset = ((int64_t)sextract32(insn, 5, 19) << 2) | extract32(insn, 29, 2);
+ rd = extract32(insn, 0, 5);
+ base = s->pc - 4;
+
+ if (page) {
+ /* ADRP (page based) */
+ base &= ~0xfff;
+ offset <<= 12;
+ }
+
+ tcg_gen_movi_i64(cpu_reg(s, rd), base + offset);
}
/* Add/subtract (immediate) */