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authorPeter Maydell <peter.maydell@linaro.org>2014-03-08 16:13:27 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-03-09 14:00:38 +0000
commite49605ccb83ba04def1ee71355f9f1a1f428ab82 (patch)
treea9ae6ef809692cfbb0a75ec848a124f0838406c4
parent416ac204050931e086ee73fade8f180bf200eae2 (diff)
downloadqemu-arm-e49605ccb83ba04def1ee71355f9f1a1f428ab82.tar.gz
target-arm: A64: Implement FCVTN
Implement FCVTN (narrowing fp-to-fp conversions) from the SIMD 2-reg-misc category. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/translate-a64.c21
1 files changed, 20 insertions, 1 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index d0df8d2f98..a958aa632c 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -8450,13 +8450,30 @@ static void handle_2misc_narrow(DisasContext *s, int opcode, bool u, bool is_q,
genenvfn = fns[size][u];
break;
}
+ case 0x16: /* FCVTN, FCVTN2 */
+ /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
+ if (size == 3) {
+ gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, cpu_env);
+ } else {
+ TCGv_i32 tcg_lo = tcg_temp_new_i32();
+ TCGv_i32 tcg_hi = tcg_temp_new_i32();
+ tcg_gen_trunc_i64_i32(tcg_lo, tcg_op);
+ gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, cpu_env);
+ tcg_gen_shri_i64(tcg_op, tcg_op, 32);
+ tcg_gen_trunc_i64_i32(tcg_hi, tcg_op);
+ gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, cpu_env);
+ tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16);
+ tcg_temp_free_i32(tcg_lo);
+ tcg_temp_free_i32(tcg_hi);
+ }
+ break;
default:
g_assert_not_reached();
}
if (genfn) {
genfn(tcg_res[pass], tcg_op);
- } else {
+ } else if (genenvfn) {
genenvfn(tcg_res[pass], cpu_env, tcg_op);
}
@@ -8807,6 +8824,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
break;
case 0x16: /* FCVTN, FCVTN2 */
+ handle_2misc_narrow(s, opcode, 0, is_q, size, rn, rd);
+ return;
case 0x17: /* FCVTL, FCVTL2 */
case 0x18: /* FRINTN */
case 0x19: /* FRINTM */