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authorAlex Bennée <alex.bennee@linaro.org>2014-02-20 12:46:44 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-02-27 14:20:40 +0000
commite201ef7eaab3808e5de4cb7ecfb7d94a51b28acc (patch)
tree8c74c09e8fbc5bac9312fd4ef9b4578e69962cc3
parent6c13ec2a5a90e4c1a2cac33841b4aa58efd58534 (diff)
downloadqemu-arm-e201ef7eaab3808e5de4cb7ecfb7d94a51b28acc.tar.gz
target-arm: A64: Fix bug in add_sub_ext handling of rn
rn == 31 always means SP (not XZR) whether an add_sub_ext instruction is setting the flags or not; only rd has behaviour dependent on whether we are setting flags. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/translate-a64.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index f89b0a5abd..90936cd6d0 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -3096,12 +3096,11 @@ static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
/* non-flag setting ops may use SP */
if (!setflags) {
- tcg_rn = read_cpu_reg_sp(s, rn, sf);
tcg_rd = cpu_reg_sp(s, rd);
} else {
- tcg_rn = read_cpu_reg(s, rn, sf);
tcg_rd = cpu_reg(s, rd);
}
+ tcg_rn = read_cpu_reg_sp(s, rn, sf);
tcg_rm = read_cpu_reg(s, rm, sf);
ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3);