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authorPeter Maydell <peter.maydell@linaro.org>2014-02-26 17:20:05 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-02-26 17:20:05 +0000
commitcd5c11b84b2539049e0fdc2c4c5f3e86e88a8bff (patch)
tree8cb911d8c706f08864838f16906dab10def6ff01
parent0b45451e588e35965175c06b832a799a159716f0 (diff)
downloadqemu-arm-cd5c11b84b2539049e0fdc2c4c5f3e86e88a8bff.tar.gz
target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI
Define a dummy version of the AArch64 OSLAR_EL1 system register which just ignores writes. Linux will always write to this (it is the OS lock used for debugging), but we don't support debug. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-rw-r--r--target-arm/helper.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index dde389c8af..61303b6ce9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1738,6 +1738,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
+ { .name = "OSLAR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
+ .access = PL1_W, .type = ARM_CP_NOP },
REGINFO_SENTINEL
};