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authorPeter Maydell <peter.maydell@linaro.org>2014-03-08 18:05:38 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-03-09 14:00:39 +0000
commit656c16b45d3cccf93209abdbe288774025882fd4 (patch)
tree5fea7b58890e5e5ea1f84c261b8f84e34a5a0d19
parent8073eb307fb028522c42aa9ac731b099341fdc4f (diff)
downloadqemu-arm-656c16b45d3cccf93209abdbe288774025882fd4.tar.gz
target-arm: A64: List unsupported shift-imm opcodes
Add the remaining unsupported opcodes to the decode switches for the shift-imm and scalar shift-imm categories so we can see what is still to be implemented. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/translate-a64.c13
1 files changed, 11 insertions, 2 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 45f89961f8..8bf66a6def 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -6135,9 +6135,15 @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
handle_vec_simd_sqshrn(s, true, false, is_u, is_u,
immh, immb, opcode, rn, rd);
break;
- default:
+ case 0x8: /* SRI */
+ case 0xc: /* SQSHLU */
+ case 0xe: /* SQSHL, UQSHL */
+ case 0x1f: /* FCVTZS, FCVTZU */
unsupported_encoding(s, insn);
break;
+ default:
+ unallocated_encoding(s);
+ break;
}
}
@@ -7281,11 +7287,14 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb,
opcode, rn, rd);
break;
+ case 0x8: /* SRI */
+ case 0xc: /* SQSHLU */
+ case 0xe: /* SQSHL, UQSHL */
case 0x1f: /* FCVTZS/ FCVTZU */
unsupported_encoding(s, insn);
return;
default:
- unsupported_encoding(s, insn);
+ unallocated_encoding(s);
return;
}
}