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authorPeter Maydell <peter.maydell@linaro.org>2014-02-26 17:20:03 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-02-26 17:20:03 +0000
commit5ebafdf31a22069952cd6c4f4e60df1cb6a6a22e (patch)
treef3debbb335a49984dc76822281d9da13cae4133a
parentb0fe2427511232f361942f672511970e5c75eb4b (diff)
downloadqemu-arm-5ebafdf31a22069952cd6c4f4e60df1cb6a6a22e.tar.gz
target-arm: Implement AArch64 SCTLR_EL1
Implement the AArch64 view of the system control register SCTLR_EL1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-rw-r--r--target-arm/cpu.h2
-rw-r--r--target-arm/helper.c3
2 files changed, 3 insertions, 2 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 51fa63497e..74b1122927 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -169,7 +169,7 @@ typedef struct CPUARMState {
struct {
uint32_t c0_cpuid;
uint64_t c0_cssel; /* Cache size selection. */
- uint32_t c1_sys; /* System control register. */
+ uint64_t c1_sys; /* System control register. */
uint32_t c1_coproc; /* Coprocessor access register. */
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
uint32_t c1_scr; /* secure config register. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e230a189a1..630ace98e9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1948,7 +1948,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
/* Generic registers whose values depend on the implementation */
{
ARMCPRegInfo sctlr = {
- .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
+ .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
.writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
.raw_writefn = raw_write,