diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-08-01 16:21:18 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-08-01 16:21:18 +0100 |
| commit | 5265d24c981dfdda8d29b44f7e84a514da75eedc (patch) | |
| tree | cc825c23bb2ae3c3ab8c99b344420a2bd70a6a56 | |
| parent | b9e8d68a3982a470b1d42abda90fcd46c01b52bc (diff) | |
target/arm: Move sve probe inside kvm >= 4.15 branchpull-target-arm-20220801
The test for the IF block indicates no ID registers are exposed, much
less host support for SVE. Move the SVE probe into the ELSE block.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220726045828.53697-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/kvm64.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 43cd7eb890..9b9dd46d78 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -679,18 +679,18 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, ARM64_SYS_REG(3, 3, 9, 12, 0)); } - } - if (sve_supported) { - /* - * There is a range of kernels between kernel commit 73433762fcae - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled - * SVE support, which resulted in an error rather than RAZ. - * So only read the register if we set KVM_ARM_VCPU_SVE above. - */ - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, - ARM64_SYS_REG(3, 0, 0, 4, 4)); + if (sve_supported) { + /* + * There is a range of kernels between kernel commit 73433762fcae + * and f81cb2c3ad41 which have a bug where the kernel doesn't + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has + * enabled SVE support, which resulted in an error rather than RAZ. + * So only read the register if we set KVM_ARM_VCPU_SVE above. + */ + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, + ARM64_SYS_REG(3, 0, 0, 4, 4)); + } } kvm_arm_destroy_scratch_host_vcpu(fdarray); |