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authorPeter Maydell <peter.maydell@linaro.org>2014-01-26 00:53:25 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-01-26 19:08:24 +0000
commit6aa24918821e5676513a57d8b4859a0b1506ac65 (patch)
treea558d6641a5ff26f94d7031bd3fc9d3e63fc31c1
parentfdb8bdfa65addecc65ad66adc3118284b4137fcd (diff)
downloadqemu-arm-6aa24918821e5676513a57d8b4859a0b1506ac65.tar.gz
target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT
Implement the 2-reg-misc CNT, NOT and RBIT instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/helper.h1
-rw-r--r--target-arm/neon_helper.c12
-rw-r--r--target-arm/translate-a64.c34
3 files changed, 41 insertions, 6 deletions
diff --git a/target-arm/helper.h b/target-arm/helper.h
index 70872dffc6..a3c507e2fa 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -319,6 +319,7 @@ DEF_HELPER_1(neon_cls_s8, i32, i32)
DEF_HELPER_1(neon_cls_s16, i32, i32)
DEF_HELPER_1(neon_cls_s32, i32, i32)
DEF_HELPER_1(neon_cnt_u8, i32, i32)
+DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i32, i32)
DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32)
DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32)
diff --git a/target-arm/neon_helper.c b/target-arm/neon_helper.c
index be6fbd997e..b4c86904f4 100644
--- a/target-arm/neon_helper.c
+++ b/target-arm/neon_helper.c
@@ -1133,6 +1133,18 @@ uint32_t HELPER(neon_cnt_u8)(uint32_t x)
return x;
}
+/* Reverse bits in each 8 bit word */
+uint32_t HELPER(neon_rbit_u8)(uint32_t x)
+{
+ x = ((x & 0xf0f0f0f0) >> 4)
+ | ((x & 0x0f0f0f0f) << 4);
+ x = ((x & 0x88888888) >> 3)
+ | ((x & 0x44444444) >> 1)
+ | ((x & 0x22222222) << 1)
+ | ((x & 0x11111111) << 3);
+ return x;
+}
+
#define NEON_QDMULH16(dest, src1, src2, round) do { \
uint32_t tmp = (int32_t)(int16_t) src1 * (int16_t) src2; \
if ((tmp ^ (tmp << 1)) & SIGNBIT) { \
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index d484967219..3a3489b841 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -6250,6 +6250,12 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
TCGCond cond;
switch (opcode) {
+ case 0x5: /* NOT */
+ /* This opcode is shared with CNT and RBIT but we have earlier
+ * enforced that size == 3 if and only if this is the NOT insn.
+ */
+ tcg_gen_not_i64(tcg_rd, tcg_rn);
+ break;
case 0xa: /* CMLT */
/* 64 bit integer comparison against zero, result is
* test ? (2^64 - 1) : 0. We implement via setcond(!test) and
@@ -7413,13 +7419,19 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x1: /* REV16 */
unsupported_encoding(s, insn);
return;
- case 0x5: /* CNT, NOT, RBIT */
- if ((u == 0 && size > 0) ||
- (u == 1 && size > 1)) {
- unallocated_encoding(s);
- return;
+ case 0x5: /* CNT, NOT, RBIT */
+ if (u && size == 0) {
+ /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
+ size = 3;
+ break;
+ } else if (u && size == 1) {
+ /* RBIT */
+ break;
+ } else if (!u && size == 0) {
+ /* CNT */
+ break;
}
- unsupported_encoding(s, insn);
+ unallocated_encoding(s);
return;
case 0x2: /* SADDLP, UADDLP */
case 0x4: /* CLS, CLZ */
@@ -7581,6 +7593,16 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
} else {
/* Use helpers for 8 and 16 bit elements */
switch (opcode) {
+ case 0x5: /* CNT, RBIT */
+ /* For these two insns size is part of the opcode specifier
+ * (handled earlier); they always operate on byte elements.
+ */
+ if (u) {
+ gen_helper_neon_rbit_u8(tcg_res, tcg_op);
+ } else {
+ gen_helper_neon_cnt_u8(tcg_res, tcg_op);
+ }
+ break;
case 0x8: /* CMGT, CMGE */
case 0x9: /* CMEQ, CMLE */
case 0xa: /* CMLT */