diff options
| author | Claudio Fontana <claudio.fontana@linaro.org> | 2013-12-03 15:12:19 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-12-03 21:19:20 +0000 |
| commit | 8ff4c2f2c873cc3dc85cec580b6c6f4c51d59e01 (patch) | |
| tree | b2c1f52149cd561fc20d452dbdfd3a96388edd17 | |
| parent | d41620e6d9cbc25c4ccae539847a1c4c0a5d4ca9 (diff) | |
target-arm: A64: add support for ADR and ADRP
this adds support for the instructions described in:
C3.4.6 PC-rel. addressing (ADR and ADRP).
Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: adapted to new decoder structure]
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
from Alexander Graf <agraf@suse.de> aarch64 series 26/60
| -rw-r--r-- | target-arm/translate-a64.c | 24 |
1 files changed, 22 insertions, 2 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index a6496b5c5c..cebdc6dddb 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -630,10 +630,30 @@ static void disas_ldst(DisasContext *s, uint32_t insn) } } -/* PC-rel. addressing */ +/* C3.4.6 PC-rel. addressing */ + static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + /* + * 31 30 29 28 27 26 25 24 23 5 4 0 + * op immlo 1 0 0 0 0 immhi Rd + */ + unsigned int page, rd; /* op -> page */ + uint64_t base; + int64_t offset; /* SignExtend(immhi:immlo) -> offset */ + + page = insn & (1 << 31) ? 1 : 0; + offset = ((int64_t)sextract32(insn, 5, 19) << 2) | extract32(insn, 29, 2); + rd = extract32(insn, 0, 5); + base = s->pc - 4; + + if (page) { + /* ADRP (page based) */ + base &= ~0xfff; + offset <<= 12; /* apply Zeros */ + } + + tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); } /* Add/subtract (immediate) */ |