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authorPeter Maydell <peter.maydell@linaro.org>2012-07-03 09:58:09 +0000
committerPeter Maydell <peter.maydell@linaro.org>2012-07-03 09:58:09 +0000
commitf1aa3b38504c83204e2f9e4e7d6f02f1d394ae68 (patch)
tree8dff4d29852e29c6d4af59538a7c54af3a3d63a0
parent71ea2e016131a9fcde6f1ffd3e0e34a64c21f593 (diff)
downloadqemu-arm-f1aa3b38504c83204e2f9e4e7d6f02f1d394ae68.tar.gz
hw/cadence_gem: Make rx_desc_addr and tx_desc_addr uint32_t
Make the state fields rx_desc_addr and tx_desc_addr uint32_t; this matches the VMStateDescription, and also conforms to how hardware works: the registers don't magically become larger if the device is attached to a CPU with a larger physical address size. It also fixes a compile failure if the target_phys_addr_t type is changed to 64 bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
-rw-r--r--hw/cadence_gem.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/cadence_gem.c b/hw/cadence_gem.c
index dbde3920d0..87143caf2d 100644
--- a/hw/cadence_gem.c
+++ b/hw/cadence_gem.c
@@ -339,8 +339,8 @@ typedef struct {
uint8_t phy_loop; /* Are we in phy loopback? */
/* The current DMA descriptor pointers */
- target_phys_addr_t rx_desc_addr;
- target_phys_addr_t tx_desc_addr;
+ uint32_t rx_desc_addr;
+ uint32_t tx_desc_addr;
} GemState;