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authorPeter Maydell <peter.maydell@linaro.org>2012-07-05 10:59:13 +0000
committerPeter Maydell <peter.maydell@linaro.org>2012-07-05 11:01:45 +0000
commite4db394f67435c8a96e0c826379ec619658bd083 (patch)
tree9fd988f51bf2529c4939f40cfd5f9bc9975576ff
parent5bad9d00e92d60ab0b1bdebecf78aed7f31e1edc (diff)
downloadqemu-arm-e4db394f67435c8a96e0c826379ec619658bd083.tar.gz
target-arm: Fix TCG temp handling in 64 bit cp writes
Fix errors in the TCG temp handling in the 64 bit coprocessor write path: we were reusing a 32 bit temp after it had been freed by store_reg(), and failing to free a 64 bit temp. This bug has no visible effect at this point because there aren't any non-NOP 64 bit registers yet; it needs to be fixed as a prerequisite for the 64 bit registers in LPAE support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/translate.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index a2a0ecddad..64d7cfdf30 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -6263,7 +6263,9 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
tcg_gen_trunc_i64_i32(tmp, tmp64);
store_reg(s, rt, tmp);
tcg_gen_shri_i64(tmp64, tmp64, 32);
+ tmp = tcg_temp_new_i32();
tcg_gen_trunc_i64_i32(tmp, tmp64);
+ tcg_temp_free_i64(tmp64);
store_reg(s, rt2, tmp);
} else {
TCGv tmp;