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-rw-r--r--arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi7
-rw-r--r--arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi122
-rw-r--r--arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi78
-rw-r--r--arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi62
-rw-r--r--arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi370
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-pins.dtsi76
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916.dtsi216
-rw-r--r--arch/arm64/boot/dts/qcom/msm8996-pins.dtsi303
-rw-r--r--arch/arm64/boot/dts/qcom/msm8996.dtsi1180
-rw-r--r--arch/arm64/boot/dts/qcom/pm8916.dtsi126
-rw-r--r--arch/arm64/boot/dts/qcom/pm8994.dtsi6
-rw-r--r--arch/arm64/boot/dts/qcom/pmi8994.dtsi31
12 files changed, 2541 insertions, 36 deletions
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
index ec2f0de67993..16c1f1b07c51 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
@@ -32,16 +32,15 @@
};
&pm8916_mpps {
-
- pinctrl-names = "default";
- pinctrl-0 = <&ls_exp_gpio_f>;
-
ls_exp_gpio_f: pm8916_mpp4 {
pinconf {
pins = "mpp4";
function = "digital";
output-low;
power-source = <PM8916_MPP_L5>; // 1.8V
+
+ /* PWM signal is available on DTEST 1 */
+ qcom,dtest = <1>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 1d63e6b879de..4c3dda5f3a83 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -174,6 +174,7 @@
label = "apq8016-sbc:green:user4";
gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "none";
+ panic-indicator;
default-state = "off";
};
@@ -329,9 +330,130 @@
};
};
+ spmi@200f000 {
+ pm8916@1 {
+ pwm@bc00 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ls_exp_gpio_f>;
+ };
+ };
+ };
+
wcnss@a21b000 {
status = "okay";
};
+
+ camera_vdddo_1v8: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera_vdddo";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ camera_vdda_2v8: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera_vdda";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ camera_vddd_1v5: fixedregulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera_vddd";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
+ cci@1b0c000 {
+ status = "ok";
+
+ camera_rear@3b {
+ compatible = "ovti,ov5645";
+ reg = <0x3b>;
+
+ enable-gpios = <&msmgpio 34 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&camera_rear_default>;
+
+ clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "xclk";
+ clock-frequency = <23880000>;
+
+ vdddo-supply = <&camera_vdddo_1v8>;
+ vdda-supply = <&camera_vdda_2v8>;
+ vddd-supply = <&camera_vddd_1v5>;
+
+ status = "disabled";
+
+ port {
+ ov5645_ep: endpoint {
+ clock-lanes = <1>;
+ data-lanes = <0 2>;
+ remote-endpoint = <&csiphy0_ep>;
+ };
+ };
+ };
+
+ camera_front@3a {
+ compatible = "ovti,ov5645";
+ reg = <0x3a>;
+
+ enable-gpios = <&msmgpio 33 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&msmgpio 28 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&camera_front_default>;
+
+ clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
+ clock-names = "xclk";
+ clock-frequency = <23880000>;
+
+ vdddo-supply = <&camera_vdddo_1v8>;
+ vdda-supply = <&camera_vdda_2v8>;
+ vddd-supply = <&camera_vddd_1v5>;
+
+ status = "disabled";
+
+ port {
+ ov5645_2_ep: endpoint {
+ clock-lanes = <1>;
+ data-lanes = <0 2>;
+ remote-endpoint = <&csiphy1_ep>;
+ };
+ };
+ };
+ };
+
+ camss@1b00000 {
+ status = "ok";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ csiphy0_ep: endpoint {
+ clock-lanes = <1>;
+ data-lanes = <0 2>;
+ remote-endpoint = <&ov5645_ep>;
+ status = "disabled";
+ };
+ };
+ port@1 {
+ reg = <1>;
+ csiphy1_ep: endpoint {
+ clock-lanes = <1>;
+ data-lanes = <0 2>;
+ remote-endpoint = <&ov5645_2_ep>;
+ status = "disabled";
+ };
+ };
+ };
+ };
};
usb2513 {
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi
index 24552f19b3fa..43c3a99a3d2a 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi
@@ -36,4 +36,82 @@
drive-strength = <2>; /* 2 MA */
};
};
+
+ hdmi_hpd_active: hdmi_hpd_active {
+ mux {
+ pins = "gpio34";
+ function = "hdmi_hot";
+ };
+
+ config {
+ pins = "gpio34";
+ bias-pull-down;
+ drive-strength = <16>;
+ };
+ };
+
+ hdmi_hpd_suspend: hdmi_hpd_suspend {
+ mux {
+ pins = "gpio34";
+ function = "hdmi_hot";
+ };
+
+ config {
+ pins = "gpio34";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+ };
+
+ hdmi_ddc_active: hdmi_ddc_active {
+ mux {
+ pins = "gpio32", "gpio33";
+ function = "hdmi_ddc";
+ };
+
+ config {
+ pins = "gpio32", "gpio33";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ hdmi_ddc_suspend: hdmi_ddc_suspend {
+ mux {
+ pins = "gpio32", "gpio33";
+ function = "hdmi_ddc";
+ };
+
+ config {
+ pins = "gpio32", "gpio33";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ blsp1_uart1_default: blsp1_uart1_default {
+ mux {
+ pins = "gpio41", "gpio42", "gpio43", "gpio44";
+ function = "blsp_uart2";
+ };
+
+ config {
+ pins = "gpio41", "gpio42", "gpio43", "gpio44";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ blsp1_uart1_sleep: blsp1_uart1_sleep {
+ mux {
+ pins = "gpio41", "gpio42", "gpio43", "gpio44";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio41", "gpio42", "gpio43", "gpio44";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
index 59b29ddfb6e9..7c65950658c6 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
@@ -4,7 +4,7 @@
&pm8994_gpios {
pinctrl-names = "default";
- pinctrl-0 = <&ls_exp_gpio_f>;
+ pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>;
ls_exp_gpio_f: pm8994_gpio5 {
pinconf {
@@ -14,6 +14,28 @@
};
};
+ bt_en_gpios: bt_en_gpios {
+ pinconf {
+ pins = "gpio19";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ output-low;
+ power-source = <PM8994_GPIO_S4>; // 1.8V
+ qcom,drive-strength = <3>;
+ bias-pull-down;
+ };
+ };
+
+ wlan_en_gpios: wlan_en_gpios {
+ pinconf {
+ pins = "gpio8";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ output-low;
+ power-source = <PM8994_GPIO_S4>; // 1.8V
+ qcom,drive-strength = <3>;
+ bias-pull-down;
+ };
+ };
+
volume_up_gpio: pm8996_gpio2 {
pinconf {
pins = "gpio2";
@@ -26,6 +48,16 @@
};
};
+ divclk4_pin_a: divclk4 {
+ pinconf {
+ pins = "gpio18";
+ function = PMIC_GPIO_FUNC_FUNC2;
+
+ bias-disable;
+ power-source = <PM8994_GPIO_S4>;
+ };
+ };
+
usb3_vbus_det_gpio: pm8996_gpio22 {
pinconf {
pins = "gpio22";
@@ -50,3 +82,31 @@
};
};
};
+
+&pm8994_mpps {
+ pm8994_mpp2_wifi_led: mpp2-wifi-led-active {
+ pins = "mpp2";
+ function = "sink";
+
+ output-low;
+ qcom,dtest = <1>;
+ };
+
+ pm8994_mpp4_bt_led: mpp4-wifi-led-active {
+ pins = "mpp4";
+ function = "sink";
+
+ output-low;
+ qcom,dtest = <2>;
+ };
+};
+
+&pmi8994_mpps {
+ pmi8994_mpp2_userled4: mpp2-userled4 {
+ pins = "mpp2";
+ function = "sink";
+
+ output-low;
+ qcom,dtest = <4>;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 789f3e87321e..6d43751d9db8 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -18,11 +18,13 @@
#include "apq8096-db820c-pmic-pins.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
-
+#include <dt-bindings/sound/qcom,q6afe.h>
+#include <dt-bindings/sound/qcom,q6asm.h>
/ {
aliases {
serial0 = &blsp2_uart1;
serial1 = &blsp2_uart2;
+ serial2 = &blsp1_uart1;
i2c0 = &blsp1_i2c2;
i2c1 = &blsp2_i2c1;
i2c2 = &blsp2_i2c0;
@@ -34,7 +36,36 @@
stdout-path = "serial0:115200n8";
};
+ clocks {
+ divclk4: divclk4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "divclk4";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&divclk4_pin_a>;
+ };
+ };
+
soc {
+ serial@7570000 {
+ label = "BT-UART";
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_uart1_default>;
+ pinctrl-1 = <&blsp1_uart1_sleep>;
+
+ bluetooth {
+ compatible = "qcom,qca6174-bt";
+
+ /* bt_disable_n gpio */
+ enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
+
+ clocks = <&divclk4>;
+ };
+ };
+
serial@75b0000 {
label = "LS-UART1";
status = "okay";
@@ -43,13 +74,13 @@
pinctrl-1 = <&blsp2_uart1_2pins_sleep>;
};
- serial@75b1000 {
- label = "LS-UART0";
- status = "okay";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_uart2_4pins_default>;
- pinctrl-1 = <&blsp2_uart2_4pins_sleep>;
- };
+// serial@75b1000 {
+// label = "LS-UART0";
+// status = "okay";
+// pinctrl-names = "default", "sleep";
+// pinctrl-0 = <&blsp2_uart2_4pins_default>;
+// pinctrl-1 = <&blsp2_uart2_4pins_sleep>;
+// };
i2c@07577000 {
/* On Low speed expansion */
@@ -87,6 +118,8 @@
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
cd-gpios = <&msmgpio 38 0x1>;
+ vmmc-supply = <&pm8994_l21>;
+ vqmmc-supply = <&pm8994_l13>;
status = "okay";
};
@@ -138,6 +171,223 @@
pinctrl-names = "default";
pinctrl-0 = <&usb2_vbus_det_gpio>;
};
+
+ ufsphy@627000 {
+ status = "okay";
+ };
+
+ ufshc@624000 {
+ status = "okay";
+ };
+
+ wlan_en: wlan-en-1-8v {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_en_gpios>;
+ compatible = "regulator-fixed";
+ regulator-name = "wlan-en-regulator";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&pm8994_gpios 8 0>;
+
+ /* WLAN card specific delay */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+
+ agnoc@0 {
+ qcom,pcie@00600000 {
+ status = "okay";
+ perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;
+ vddpe-3v3-supply = <&wlan_en>;
+
+ };
+
+ qcom,pcie@00608000 {
+ status = "okay";
+ perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;
+ };
+
+ qcom,pcie@00610000 {
+ status = "okay";
+ perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ mdss@900000 {
+ status = "okay";
+
+ mdp@901000 {
+ status = "okay";
+ };
+
+ hdmi-phy@9a0600 {
+ status = "okay";
+
+ vddio-supply = <&pm8994_l12>;
+ vcca-supply = <&pm8994_l28>;
+ };
+
+ hdmi-tx@9a0000 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
+ pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
+
+ core-vdda-supply = <&pm8994_l12>;
+ core-vcc-supply = <&pm8994_s4>;
+ #sound-dai-cells = <1>;
+ };
+ };
+
+ camera_vdddo_1v8: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera_vdddo";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ camera_vdda_2v8: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera_vdda";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ camera_vddd_1v5: fixedregulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "camera_vddd";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
+ cci@a0c000 {
+ status = "ok";
+
+ camera_rear@60 {
+ compatible = "ovti,ov7251";
+ reg = <0x60>;
+
+ enable-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&camera_rear_default>;
+
+ clocks = <&mmcc CAMSS_MCLK0_CLK>;
+ clock-names = "xclk";
+ clock-frequency = <24000000>;
+
+ vdddo-supply = <&camera_vdddo_1v8>;
+ vdda-supply = <&camera_vdda_2v8>;
+ vddd-supply = <&camera_vddd_1v5>;
+
+ status = "disabled";
+
+ port {
+ ov7251_ep: endpoint {
+ clock-lanes = <1>;
+ data-lanes = <0>;
+ remote-endpoint = <&csiphy0_ep>;
+ };
+ };
+ };
+
+ camera_board@39 {
+ compatible = "ovti,ov5645";
+ reg = <0x39>;
+
+ enable-gpios = <&msmgpio 98 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&msmgpio 104 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&camera_board_default>;
+
+ clocks = <&mmcc CAMSS_MCLK1_CLK>;
+ clock-names = "xclk";
+ clock-frequency = <24000000>;
+
+ vdddo-supply = <&camera_vdddo_1v8>;
+ vdda-supply = <&camera_vdda_2v8>;
+ vddd-supply = <&camera_vddd_1v5>;
+
+ status = "disabled";
+
+ port {
+ ov5645_2_ep: endpoint {
+ clock-lanes = <1>;
+ data-lanes = <0 2>;
+ remote-endpoint = <&csiphy1_ep>;
+ };
+ };
+ };
+
+ camera_front@3a {
+ compatible = "ovti,ov5645";
+ reg = <0x3a>;
+
+ enable-gpios = <&msmgpio 133 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&msmgpio 23 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&camera_front_default>;
+
+ clocks = <&mmcc CAMSS_MCLK2_CLK>;
+ clock-names = "xclk";
+ clock-frequency = <24000000>;
+
+ vdddo-supply = <&camera_vdddo_1v8>;
+ vdda-supply = <&camera_vdda_2v8>;
+ vddd-supply = <&camera_vddd_1v5>;
+
+ status = "disabled";
+
+ port {
+ ov5645_3_ep: endpoint {
+ clock-lanes = <1>;
+ data-lanes = <0 2>;
+ remote-endpoint = <&csiphy2_ep>;
+ };
+ };
+ };
+ };
+
+ camss@a00000 {
+ status = "ok";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ csiphy0_ep: endpoint {
+ clock-lanes = <7>;
+ data-lanes = <0>;
+ remote-endpoint = <&ov7251_ep>;
+ status = "disabled";
+ };
+ };
+ port@1 {
+ reg = <1>;
+ csiphy1_ep: endpoint {
+ clock-lanes = <7>;
+ data-lanes = <0 1>;
+ remote-endpoint = <&ov5645_2_ep>;
+ status = "disabled";
+ };
+ };
+ port@2 {
+ reg = <2>;
+ csiphy2_ep: endpoint {
+ clock-lanes = <7>;
+ data-lanes = <0 1>;
+ remote-endpoint = <&ov5645_3_ep>;
+ status = "disabled";
+ };
+ };
+ };
+ };
};
@@ -305,3 +555,107 @@
};
};
};
+
+&spmi_bus {
+ pmic@1 {
+ lpg {
+ status = "okay";
+
+ qcom,dtest = <1 2>,
+ <2 2>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pm8994_mpp2_wifi_led>, <&pm8994_mpp4_bt_led>;
+
+ wifi-led {
+ led-sources = <1>;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+
+ bt-led {
+ led-sources = <2>;
+ linux,default-trigger = "hci0-power";
+ default-state = "off";
+ };
+ };
+ };
+
+ pmic@3 {
+ lpg@b100 {
+ qcom,power-source = <1>;
+
+ qcom,dtest = <0 0>,
+ <0 0>,
+ <0 0>,
+ <4 1>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmi8994_mpp2_userled4>;
+
+ status = "okay";
+
+ user0 {
+ led-sources = <2>;
+
+ label = "db820c:green:user0";
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ user1 {
+ led-sources = <1>;
+
+ label = "db820c:green:user1";
+ };
+
+ user2 {
+ led-sources = <3>;
+
+ label = "db820c:green:user2";
+ };
+
+ user3 {
+ led-sources = <4>;
+
+ label = "db820c:green:user3";
+
+ qcom,dtest = <4 1>;
+ };
+ };
+ };
+};
+&sound {
+ compatible = "qcom,apq8096-sndcard";
+ qcom,model = "DB820c";
+ qcom,audio-routing =
+ "RX_BIAS", "MCLK";
+ mm1-dai-link {
+ link-name = "MultiMedia1";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
+ };
+ platform {
+ sound-dai = <&q6asmdai>;
+ };
+ };
+
+ hdmi-dai-link {
+ link-name = "HDMI Playback";
+ cpu {
+ sound-dai = <&q6afedai HDMI_RX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&hdmi 0>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
index 4cb0b5834143..b1ed8dcf7543 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -733,4 +733,80 @@
bias-pull-up;
};
};
+
+ cci0_default: cci0_default {
+ pinmux {
+ function = "cci_i2c";
+ pins = "gpio29", "gpio30";
+ };
+ pinconf {
+ pins = "gpio29", "gpio30";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ camera_front_default: camera_front_default {
+ pinmux_pwdn {
+ function = "gpio";
+ pins = "gpio33";
+ };
+ pinconf_pwdn {
+ pins = "gpio33";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ pinmux_rst {
+ function = "gpio";
+ pins = "gpio28";
+ };
+ pinconf_rst {
+ pins = "gpio28";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ pinmux_mclk1 {
+ function = "cam_mclk1";
+ pins = "gpio27";
+ };
+ pinconf_mclk1 {
+ pins = "gpio27";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ camera_rear_default: camera_rear_default {
+ pinmux_pwdn {
+ function = "gpio";
+ pins = "gpio34";
+ };
+ pinconf_pwdn {
+ pins = "gpio34";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ pinmux_rst {
+ function = "gpio";
+ pins = "gpio35";
+ };
+ pinconf_rst {
+ pins = "gpio35";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ pinmux_mclk0 {
+ function = "cam_mclk0";
+ pins = "gpio26";
+ };
+ pinconf_mclk0 {
+ pins = "gpio26";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 61da6e65900b..3b28b28e2759 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/reset/qcom,gcc-msm8916.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
model = "Qualcomm Technologies, Inc. MSM8916";
@@ -69,8 +70,11 @@
};
rmtfs@86700000 {
+ compatible = "qcom,rmtfs-mem";
reg = <0x0 0x86700000 0x0 0xe0000>;
no-map;
+
+ qcom,client-id = <1>;
};
rfsa@867e00000 {
@@ -110,6 +114,14 @@
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
+ clocks = <&apcs 0>;
+ clock-latency = <200000>;
+ cpu-supply = <&pm8916_spmi_s2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ /* cooling options */
+ cooling-min-level = <0>;
+ cooling-max-level = <7>;
+ #cooling-cells = <2>;
};
CPU1: cpu@1 {
@@ -119,6 +131,14 @@
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
+ clocks = <&apcs 0>;
+ clock-latency = <200000>;
+ cpu-supply = <&pm8916_spmi_s2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ /* cooling options */
+ cooling-min-level = <0>;
+ cooling-max-level = <7>;
+ #cooling-cells = <2>;
};
CPU2: cpu@2 {
@@ -128,6 +148,14 @@
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
+ clocks = <&apcs 0>;
+ clock-latency = <200000>;
+ cpu-supply = <&pm8916_spmi_s2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ /* cooling options */
+ cooling-min-level = <0>;
+ cooling-max-level = <7>;
+ #cooling-cells = <2>;
};
CPU3: cpu@3 {
@@ -137,6 +165,14 @@
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
+ clocks = <&apcs 0>;
+ clock-latency = <200000>;
+ cpu-supply = <&pm8916_spmi_s2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ /* cooling options */
+ cooling-min-level = <0>;
+ cooling-max-level = <7>;
+ #cooling-cells = <2>;
};
L2_0: l2-cache {
@@ -161,6 +197,21 @@
method = "smc";
};
+ /*
+ * The CPR driver reads the initial voltage settings in efuse
+ * and populates OPPs.
+ */
+ cpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1050000>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
@@ -185,6 +236,13 @@
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu-thermal1 {
@@ -205,6 +263,13 @@
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
};
@@ -257,6 +322,8 @@
clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
clock-names = "core", "bus", "iface";
#reset-cells = <1>;
+
+ qcom,dload-mode = <&tcsr 0x6100>;
};
};
@@ -321,9 +388,18 @@
status = "disabled";
};
- apcs: syscon@b011000 {
- compatible = "syscon";
- reg = <0x0b011000 0x1000>;
+ a53pll: clock@b016000 {
+ compatible = "qcom,msm8916-a53pll";
+ reg = <0xb016000 0x40>;
+ #clock-cells = <0>;
+ };
+
+ apcs: mailbox@b011000 {
+ compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
+ reg = <0xb011000 0x1000>;
+ #mbox-cells = <1>;
+ clocks = <&a53pll>;
+ #clock-cells = <0>;
};
blsp1_uart2: serial@78b0000 {
@@ -722,6 +798,13 @@
clock-names = "iface", "bus";
qcom,iommu-secure-id = <17>;
+ // vfe:
+ iommu-ctx@3000 {
+ compatible = "qcom,msm-iommu-v1-sec";
+ reg = <0x3000 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
// mdp_0:
iommu-ctx@4000 {
compatible = "qcom,msm-iommu-v1-ns";
@@ -942,7 +1025,7 @@
qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
- status = "disabled";
+ status = "okay";
mba {
memory-region = <&mba_mem>;
@@ -1326,6 +1409,131 @@
compatible = "venus-encoder";
};
};
+
+ uqfprom: eeprom@58000 {
+ compatible = "qcom,qfprom-msm8916";
+ reg = <0x58000 0x7000>;
+ };
+
+ cpr@b018000 {
+ compatible = "qcom,cpr";
+ reg = <0xb018000 0x1000>;
+ interrupts = <0 15 1>, <0 16 1>, <0 17 1>;
+ vdd-mx-supply = <&pm8916_l3>;
+ acc-syscon = <&tcsr>;
+ eeprom = <&uqfprom>;
+
+ qcom,cpr-ref-clk = <19200>;
+ qcom,cpr-timer-delay-us = <5000>;
+ qcom,cpr-timer-cons-up = <0>;
+ qcom,cpr-timer-cons-down = <2>;
+ qcom,cpr-up-threshold = <0>;
+ qcom,cpr-down-threshold = <2>;
+ qcom,cpr-idle-clocks = <15>;
+ qcom,cpr-gcnt-us = <1>;
+ qcom,vdd-apc-step-up-limit = <1>;
+ qcom,vdd-apc-step-down-limit = <1>;
+ qcom,cpr-cpus = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ };
+
+ cci: cci@1b0c000 {
+ compatible = "qcom,cci-v1.0.8";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1b0c000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_CCI_AHB_CLK>,
+ <&gcc GCC_CAMSS_CCI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb",
+ "cci_ahb",
+ "cci",
+ "camss_ahb";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cci0_default>;
+ status = "disabled";
+ };
+
+ camss: camss@1b00000 {
+ compatible = "qcom,msm8916-camss";
+ reg = <0x1b0ac00 0x200>,
+ <0x1b00030 0x4>,
+ <0x1b0b000 0x200>,
+ <0x1b00038 0x4>,
+ <0x1b08000 0x100>,
+ <0x1b08400 0x100>,
+ <0x1b0a000 0x500>,
+ <0x1b00020 0x10>,
+ <0x1b10000 0x1000>;
+ reg-names = "csiphy0",
+ "csiphy0_clk_mux",
+ "csiphy1",
+ "csiphy1_clk_mux",
+ "csid0",
+ "csid1",
+ "ispif",
+ "csi_clk_mux",
+ "vfe0";
+ interrupts = <GIC_SPI 78 0>,
+ <GIC_SPI 79 0>,
+ <GIC_SPI 51 0>,
+ <GIC_SPI 52 0>,
+ <GIC_SPI 55 0>,
+ <GIC_SPI 57 0>;
+ interrupt-names = "csiphy0",
+ "csiphy1",
+ "csid0",
+ "csid1",
+ "ispif",
+ "vfe0";
+ power-domains = <&gcc VFE_GDSC>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
+ <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
+ <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI0_CLK>,
+ <&gcc GCC_CAMSS_CSI0PHY_CLK>,
+ <&gcc GCC_CAMSS_CSI0PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI0RDI_CLK>,
+ <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI1_CLK>,
+ <&gcc GCC_CAMSS_CSI1PHY_CLK>,
+ <&gcc GCC_CAMSS_CSI1PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI1RDI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>,
+ <&gcc GCC_CAMSS_VFE0_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
+ <&gcc GCC_CAMSS_VFE_AHB_CLK>,
+ <&gcc GCC_CAMSS_VFE_AXI_CLK>;
+ clock-names = "top_ahb",
+ "ispif_ahb",
+ "csiphy0_timer",
+ "csiphy1_timer",
+ "csi0_ahb",
+ "csi0",
+ "csi0_phy",
+ "csi0_pix",
+ "csi0_rdi",
+ "csi1_ahb",
+ "csi1",
+ "csi1_phy",
+ "csi1_pix",
+ "csi1_rdi",
+ "ahb",
+ "vfe0",
+ "csi_vfe0",
+ "vfe_ahb",
+ "vfe_axi";
+ vdda-supply = <&pm8916_l2>;
+ iommus = <&apps_iommu 3>;
+ status = "disabled";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
};
smd {
diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
index 659940434842..ddbec6eca5e8 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
@@ -300,4 +300,307 @@
drive-strength = <2>; /* 2 MA */
};
};
+
+ cci0_default: cci0_default {
+ mux {
+ function = "cci_i2c";
+ pins = "gpio17", "gpio18";
+ };
+ config {
+ pins = "gpio17", "gpio18";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ pcie0_clkreq_default: pcie0_clkreq_default {
+ mux {
+ pins = "gpio36";
+ function = "pci_e0";
+ };
+
+ config {
+ pins = "gpio36";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie0_perst_default: pcie0_perst_default {
+ mux {
+ pins = "gpio35";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio35";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ pcie0_wake_default: pcie0_wake_default {
+ mux {
+ pins = "gpio37";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio37";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie0_clkreq_sleep: pcie0_clkreq_sleep {
+ mux {
+ pins = "gpio36";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio36";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ pcie0_wake_sleep: pcie0_wake_sleep {
+ mux {
+ pins = "gpio37";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio37";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ pcie1_clkreq_default: pcie1_clkreq_default {
+ mux {
+ pins = "gpio131";
+ function = "pci_e1";
+ };
+
+ config {
+ pins = "gpio131";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie1_perst_default: pcie1_perst_default {
+ mux {
+ pins = "gpio130";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio130";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ pcie1_wake_default: pcie1_wake_default {
+ mux {
+ pins = "gpio132";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio132";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ pcie1_clkreq_sleep: pcie1_clkreq_sleep {
+ mux {
+ pins = "gpio131";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio131";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ pcie1_wake_sleep: pcie1_wake_sleep {
+ mux {
+ pins = "gpio132";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio132";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ pcie2_clkreq_default: pcie2_clkreq_default {
+ mux {
+ pins = "gpio115";
+ function = "pci_e2";
+ };
+
+ config {
+ pins = "gpio115";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie2_perst_default: pcie2_perst_default {
+ mux {
+ pins = "gpio114";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio114";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ pcie2_wake_default: pcie2_wake_default {
+ mux {
+ pins = "gpio116";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio116";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ pcie2_clkreq_sleep: pcie2_clkreq_sleep {
+ mux {
+ pins = "gpio115";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio115";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ pcie2_wake_sleep: pcie2_wake_sleep {
+ mux {
+ pins = "gpio116";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio116";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ camera_board_default: camera_board_default {
+ mux_pwdn {
+ function = "gpio";
+ pins = "gpio98";
+ };
+ config_pwdn {
+ pins = "gpio98";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ mux_rst {
+ function = "gpio";
+ pins = "gpio104";
+ };
+ config_rst {
+ pins = "gpio104";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ mux_mclk1 {
+ function = "cam_mclk";
+ pins = "gpio14";
+ };
+ config_mclk1 {
+ pins = "gpio14";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ camera_front_default: camera_front_default {
+ mux_pwdn {
+ function = "gpio";
+ pins = "gpio133";
+ };
+ config_pwdn {
+ pins = "gpio133";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ mux_rst {
+ function = "gpio";
+ pins = "gpio23";
+ };
+ config_rst {
+ pins = "gpio23";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ mux_mclk2 {
+ function = "cam_mclk";
+ pins = "gpio15";
+ };
+ config_mclk2 {
+ pins = "gpio15";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ camera_rear_default: camera_rear_default {
+ mux_pwdn {
+ function = "gpio";
+ pins = "gpio26";
+ };
+ config_pwdn {
+ pins = "gpio26";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ mux_rst {
+ function = "gpio";
+ pins = "gpio25";
+ };
+ config_rst {
+ pins = "gpio25";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ mux_mclk0 {
+ function = "cam_mclk";
+ pins = "gpio13";
+ };
+ config_mclk0 {
+ pins = "gpio13";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index ab00be277c6f..5bb901fe28f1 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -13,6 +13,9 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/soc/qcom,apr.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
model = "Qualcomm Technologies, Inc. MSM8996";
@@ -40,11 +43,6 @@
no-map;
};
- slpi_region: slpi@90b00000 {
- reg = <0x0 0x90b00000 0x0 0xa00000>;
- no-map;
- };
-
venus_region: venus@90400000 {
reg = <0x0 0x90400000 0x0 0x700000>;
no-map;
@@ -74,6 +72,23 @@
reg = <0x0 0x86200000 0x0 0x2600000>;
no-map;
};
+
+ zap_shader_region: gpu@8f200000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x90b00000 0x0 0xa00000>;
+ no-map;
+ };
+
+ rmtfs@86700000 {
+ compatible = "qcom,rmtfs-mem";
+
+ size = <0x0 0x200000>;
+ alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <15>;
+ };
};
cpus {
@@ -85,6 +100,12 @@
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
+ clocks = <&kryocc 0>;
+ operating-points-v2 = <&cluster0_opp>;
+ /* cooling options */
+ cooling-min-level = <0>;
+ cooling-max-level = <15>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
@@ -97,6 +118,12 @@
compatible = "qcom,kryo";
reg = <0x0 0x1>;
enable-method = "psci";
+ clocks = <&kryocc 0>;
+ operating-points-v2 = <&cluster0_opp>;
+ /* cooling options */
+ cooling-min-level = <0>;
+ cooling-max-level = <15>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_0>;
};
@@ -105,6 +132,12 @@
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
+ clocks = <&kryocc 1>;
+ operating-points-v2 = <&cluster1_opp>;
+ /* cooling options */
+ cooling-min-level = <0>;
+ cooling-max-level = <15>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
@@ -117,6 +150,12 @@
compatible = "qcom,kryo";
reg = <0x0 0x101>;
enable-method = "psci";
+ clocks = <&kryocc 1>;
+ operating-points-v2 = <&cluster1_opp>;
+ /* cooling options */
+ cooling-min-level = <0>;
+ cooling-max-level = <15>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_1>;
};
@@ -143,6 +182,183 @@
};
};
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-307200000 {
+ opp-hz = /bits/ 64 < 307200000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-422400000 {
+ opp-hz = /bits/ 64 < 422400000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-480000000 {
+ opp-hz = /bits/ 64 < 480000000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-556800000 {
+ opp-hz = /bits/ 64 < 556800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-652800000 {
+ opp-hz = /bits/ 64 < 652800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-729600000 {
+ opp-hz = /bits/ 64 < 729600000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-844800000 {
+ opp-hz = /bits/ 64 < 844800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-960000000 {
+ opp-hz = /bits/ 64 < 960000000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1036800000 {
+ opp-hz = /bits/ 64 < 1036800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1113600000 {
+ opp-hz = /bits/ 64 < 1113600000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1190400000 {
+ opp-hz = /bits/ 64 < 1190400000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1228800000 {
+ opp-hz = /bits/ 64 < 1228800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1324800000 {
+ opp-hz = /bits/ 64 < 1324800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1401600000 {
+ opp-hz = /bits/ 64 < 1401600000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1478400000 {
+ opp-hz = /bits/ 64 < 1478400000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1593600000 {
+ opp-hz = /bits/ 64 < 1593600000 >;
+ clock-latency-ns = <200000>;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-307200000 {
+ opp-hz = /bits/ 64 < 307200000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-403200000 {
+ opp-hz = /bits/ 64 < 403200000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-480000000 {
+ opp-hz = /bits/ 64 < 480000000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-556800000 {
+ opp-hz = /bits/ 64 < 556800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-652800000 {
+ opp-hz = /bits/ 64 < 652800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-729600000 {
+ opp-hz = /bits/ 64 < 729600000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-806400000 {
+ opp-hz = /bits/ 64 < 806400000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-883200000 {
+ opp-hz = /bits/ 64 < 883200000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-940800000 {
+ opp-hz = /bits/ 64 < 940800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1036800000 {
+ opp-hz = /bits/ 64 < 1036800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1113600000 {
+ opp-hz = /bits/ 64 < 1113600000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1190400000 {
+ opp-hz = /bits/ 64 < 1190400000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1248000000 {
+ opp-hz = /bits/ 64 < 1248000000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1324800000 {
+ opp-hz = /bits/ 64 < 1324800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1401600000 {
+ opp-hz = /bits/ 64 < 1401600000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1478400000 {
+ opp-hz = /bits/ 64 < 1478400000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1555200000 {
+ opp-hz = /bits/ 64 < 1555200000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1632000000 {
+ opp-hz = /bits/ 64 < 1632000000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1708800000 {
+ opp-hz = /bits/ 64 < 1708800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1785600000 {
+ opp-hz = /bits/ 64 < 1785600000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1824000000 {
+ opp-hz = /bits/ 64 < 1824000000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1920000000 {
+ opp-hz = /bits/ 64 < 1920000000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-1996800000 {
+ opp-hz = /bits/ 64 < 1996800000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-2073600000 {
+ opp-hz = /bits/ 64 < 2073600000 >;
+ clock-latency-ns = <200000>;
+ };
+ opp-2150400000 {
+ opp-hz = /bits/ 64 < 2150400000 >;
+ clock-latency-ns = <200000>;
+ };
+
+ };
+
thermal-zones {
cpu-thermal0 {
polling-delay-passive = <250>;
@@ -151,18 +367,33 @@
thermal-sensors = <&tsens0 3>;
trips {
- cpu_alert0: trip0 {
+ cpu_alert0: cpu_alert0 {
temperature = <75000>;
hysteresis = <2000>;
+ type = "active";
+ };
+ cpu_warn0: cpu_warn0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
type = "passive";
};
-
- cpu_crit0: trip1 {
+ cpu_crit0: cpu_crit0 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT 7>;
+ };
+ map1 {
+ trip = <&cpu_warn0>;
+ cooling-device = <&CPU0 8 THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu-thermal1 {
@@ -172,18 +403,33 @@
thermal-sensors = <&tsens0 5>;
trips {
- cpu_alert1: trip0 {
+ cpu_alert1: cpu_alert1 {
temperature = <75000>;
hysteresis = <2000>;
+ type = "active";
+ };
+ cpu_warn1: cpu_warn1 {
+ temperature = <90000>;
+ hysteresis = <2000>;
type = "passive";
};
-
- cpu_crit1: trip1 {
+ cpu_crit1: cpu_crit1 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT 7>;
+ };
+ map1 {
+ trip = <&cpu_warn1>;
+ cooling-device = <&CPU0 8 THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu-thermal2 {
@@ -193,18 +439,32 @@
thermal-sensors = <&tsens0 8>;
trips {
- cpu_alert2: trip0 {
+ cpu_alert2: cpu_alert2 {
temperature = <75000>;
hysteresis = <2000>;
+ type = "active";
+ };
+ cpu_warn2: cpu_warn2 {
+ temperature = <90000>;
+ hysteresis = <2000>;
type = "passive";
};
-
- cpu_crit2: trip1 {
+ cpu_crit2: cpu_crit2 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert2>;
+ cooling-device = <&CPU2 THERMAL_NO_LIMIT 7>;
+ };
+ map1 {
+ trip = <&cpu_warn2>;
+ cooling-device = <&CPU2 8 THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu-thermal3 {
@@ -214,18 +474,33 @@
thermal-sensors = <&tsens0 10>;
trips {
- cpu_alert3: trip0 {
+ cpu_alert3: cpu_alert3 {
temperature = <75000>;
hysteresis = <2000>;
+ type = "active";
+ };
+ cpu_warn3: cpu_warn3 {
+ temperature = <90000>;
+ hysteresis = <2000>;
type = "passive";
};
-
cpu_crit3: trip1 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert3>;
+ cooling-device = <&CPU2 THERMAL_NO_LIMIT 7>;
+ };
+ map1 {
+ trip = <&cpu_warn3>;
+ cooling-device = <&CPU2 8 THERMAL_NO_LIMIT>;
+ };
+ };
};
};
@@ -261,6 +536,8 @@
firmware {
scm {
compatible = "qcom,scm-msm8996";
+
+ qcom,dload-mode = <&tcsr 0x13000>;
};
};
@@ -289,6 +566,11 @@
compatible = "qcom,rpm-msm8996";
qcom,glink-channels = "rpm_requests";
+ rpmcc: qcom,rpmcc {
+ compatible = "qcom,rpmcc-msm8996";
+ #clock-cells = <1>;
+ };
+
pm8994-regulators {
compatible = "qcom,rpm-pm8994-regulators";
@@ -338,7 +620,6 @@
pm8994_l31: l31 {};
pm8994_l32: l32 {};
};
-
};
};
@@ -355,18 +636,33 @@
tcsr_mutex_regs: syscon@740000 {
compatible = "syscon";
- reg = <0x740000 0x20000>;
+ reg = <0x740000 0x40000>;
+ };
+
+ tcsr: syscon@7a0000 {
+ compatible = "qcom,tcsr-msm8996", "syscon";
+ reg = <0x7a0000 0x18000>;
};
intc: interrupt-controller@9bc0000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x40000>;
reg = <0x09bc0000 0x10000>,
<0x09c00000 0x100000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ msi_alias0: interrupt-controller@9bd0000 {
+ compatible = "qcom,gic-msi-aliases";
+ reg = <0x9bd0000 0x1000>;
+ msi-controller;
+ arm,spi-ranges = <544 96>;
+ };
};
apcs: syscon@9820000 {
@@ -390,11 +686,21 @@
};
kryocc: clock-controller@6400000 {
- compatible = "qcom,apcc-msm8996";
+ compatible = "qcom,msm8996-apcc";
reg = <0x6400000 0x90000>;
#clock-cells = <1>;
};
+ blsp1_uart1: serial@7570000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x07570000 0x1000>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
blsp1_spi0: spi@07575000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07575000 0x600>;
@@ -819,6 +1125,795 @@
phy-names = "usb2-phy", "usb3-phy";
};
};
+
+ cci: cci@a0c000 {
+ compatible = "qcom,cci-v1.4.0";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xa0c000 0x1000>;
+ interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&mmcc CAMSS_GDSC>;
+ clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
+ <&mmcc CAMSS_CCI_AHB_CLK>,
+ <&mmcc CAMSS_CCI_CLK>,
+ <&mmcc CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb",
+ "cci_ahb",
+ "cci",
+ "camss_ahb";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cci0_default>;
+ status = "disabled";
+ };
+
+ vfe_smmu: arm,smmu@da0000 {
+ compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+ reg = <0xda0000 0x10000>;
+
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
+ clocks = <&mmcc SMMU_VFE_AHB_CLK>,
+ <&mmcc SMMU_VFE_AXI_CLK>;
+ clock-names = "iface",
+ "bus";
+ #iommu-cells = <1>;
+ status = "ok";
+ };
+
+ camss: camss@a00000 {
+ compatible = "qcom,msm8996-camss";
+ reg = <0xa34000 0x1000>,
+ <0xa00030 0x4>,
+ <0xa35000 0x1000>,
+ <0xa00038 0x4>,
+ <0xa36000 0x1000>,
+ <0xa00040 0x4>,
+ <0xa30000 0x100>,
+ <0xa30400 0x100>,
+ <0xa30800 0x100>,
+ <0xa30c00 0x100>,
+ <0xa31000 0x500>,
+ <0xa00020 0x10>,
+ <0xa10000 0x1000>,
+ <0xa14000 0x1000>;
+ reg-names = "csiphy0",
+ "csiphy0_clk_mux",
+ "csiphy1",
+ "csiphy1_clk_mux",
+ "csiphy2",
+ "csiphy2_clk_mux",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid3",
+ "ispif",
+ "csi_clk_mux",
+ "vfe0",
+ "vfe1";
+ interrupts = <GIC_SPI 78 0>,
+ <GIC_SPI 79 0>,
+ <GIC_SPI 80 0>,
+ <GIC_SPI 296 0>,
+ <GIC_SPI 297 0>,
+ <GIC_SPI 298 0>,
+ <GIC_SPI 299 0>,
+ <GIC_SPI 309 0>,
+ <GIC_SPI 314 0>,
+ <GIC_SPI 315 0>;
+ interrupt-names = "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid3",
+ "ispif",
+ "vfe0",
+ "vfe1";
+ power-domains = <&mmcc VFE0_GDSC>;
+ clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
+ <&mmcc CAMSS_ISPIF_AHB_CLK>,
+ <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
+ <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
+ <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
+ <&mmcc CAMSS_CSI0_AHB_CLK>,
+ <&mmcc CAMSS_CSI0_CLK>,
+ <&mmcc CAMSS_CSI0PHY_CLK>,
+ <&mmcc CAMSS_CSI0PIX_CLK>,
+ <&mmcc CAMSS_CSI0RDI_CLK>,
+ <&mmcc CAMSS_CSI1_AHB_CLK>,
+ <&mmcc CAMSS_CSI1_CLK>,
+ <&mmcc CAMSS_CSI1PHY_CLK>,
+ <&mmcc CAMSS_CSI1PIX_CLK>,
+ <&mmcc CAMSS_CSI1RDI_CLK>,
+ <&mmcc CAMSS_CSI2_AHB_CLK>,
+ <&mmcc CAMSS_CSI2_CLK>,
+ <&mmcc CAMSS_CSI2PHY_CLK>,
+ <&mmcc CAMSS_CSI2PIX_CLK>,
+ <&mmcc CAMSS_CSI2RDI_CLK>,
+ <&mmcc CAMSS_CSI3_AHB_CLK>,
+ <&mmcc CAMSS_CSI3_CLK>,
+ <&mmcc CAMSS_CSI3PHY_CLK>,
+ <&mmcc CAMSS_CSI3PIX_CLK>,
+ <&mmcc CAMSS_CSI3RDI_CLK>,
+ <&mmcc CAMSS_AHB_CLK>,
+ <&mmcc CAMSS_VFE0_CLK>,
+ <&mmcc CAMSS_CSI_VFE0_CLK>,
+ <&mmcc CAMSS_VFE0_AHB_CLK>,
+ <&mmcc CAMSS_VFE0_STREAM_CLK>,
+ <&mmcc CAMSS_VFE1_CLK>,
+ <&mmcc CAMSS_CSI_VFE1_CLK>,
+ <&mmcc CAMSS_VFE1_AHB_CLK>,
+ <&mmcc CAMSS_VFE1_STREAM_CLK>,
+ <&mmcc CAMSS_VFE_AHB_CLK>,
+ <&mmcc CAMSS_VFE_AXI_CLK>;
+ clock-names = "top_ahb",
+ "ispif_ahb",
+ "csiphy0_timer",
+ "csiphy1_timer",
+ "csiphy2_timer",
+ "csi0_ahb",
+ "csi0",
+ "csi0_phy",
+ "csi0_pix",
+ "csi0_rdi",
+ "csi1_ahb",
+ "csi1",
+ "csi1_phy",
+ "csi1_pix",
+ "csi1_rdi",
+ "csi2_ahb",
+ "csi2",
+ "csi2_phy",
+ "csi2_pix",
+ "csi2_rdi",
+ "csi3_ahb",
+ "csi3",
+ "csi3_phy",
+ "csi3_pix",
+ "csi3_rdi",
+ "ahb",
+ "vfe0",
+ "csi_vfe0",
+ "vfe0_ahb",
+ "vfe0_stream",
+ "vfe1",
+ "csi_vfe1",
+ "vfe1_ahb",
+ "vfe1_stream",
+ "vfe_ahb",
+ "vfe_axi";
+ vdda-supply = <&pm8994_l2>;
+ iommus = <&vfe_smmu 0>,
+ <&vfe_smmu 1>,
+ <&vfe_smmu 2>,
+ <&vfe_smmu 3>;
+ status = "disabled";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ ufsphy1: ufsphy@627000 {
+ compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
+ reg = <0x627000 0xda8>;
+ reg-names = "phy_mem";
+ #phy-cells = <0>;
+ vdda-phy-max-microamp = <18380>;
+ vdda-pll-max-microamp = <9440>;
+
+ vddp-ref-clk-supply = <&pm8994_l25>;
+ vddp-ref-clk-max-microamp = <100>;
+ vddp-ref-clk-always-on;
+ clock-names = "ref_clk_src", "ref_clk";
+ clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+ <&gcc GCC_UFS_CLKREF_CLK>;
+ status = "disabled";
+ };
+
+ ufshc@624000 {
+ compatible = "qcom,ufshc";
+ reg = <0x624000 0x2500>;
+ interrupts = <0 265 0>;
+
+ phys = <&ufsphy1>;
+ phy-names = "ufsphy";
+
+ vcc-supply = <&pm8994_l20>;
+ vccq-supply = <&pm8994_l25>;
+ vccq2-supply = <&pm8994_s4>;
+
+ vcc-max-microamp = <600000>;
+ vccq-max-microamp = <450000>;
+ vccq2-max-microamp = <450000>;
+
+ power-domains = <&gcc UFS_GDSC>;
+
+ clock-names =
+ "core_clk_src",
+ "core_clk",
+ "bus_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro_src",
+ "core_clk_unipro",
+ "core_clk_ice",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk";
+ clocks =
+ <&gcc UFS_AXI_CLK_SRC>,
+ <&gcc GCC_UFS_AXI_CLK>,
+ <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
+ <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
+ <&gcc GCC_UFS_AHB_CLK>,
+ <&gcc UFS_ICE_CORE_CLK_SRC>,
+ <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
+ <&gcc GCC_UFS_ICE_CORE_CLK>,
+ <&rpmcc RPM_SMD_LN_BB_CLK>,
+ <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
+ freq-table-hz =
+ <100000000 200000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <150000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+
+ lanes-per-direction = <1>;
+ status = "disabled";
+
+ ufs_variant {
+ compatible = "qcom,ufs_variant";
+ };
+ };
+
+ agnoc@0 {
+ power-domains = <&gcc AGGRE0_NOC_GDSC>;
+ compatible = "simple-pm-bus";
+ clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
+ <&gcc GCC_AGGRE0_CNOC_AHB_CLK>,
+ <&gcc GCC_SMMU_AGGRE0_AXI_CLK>;
+
+ clock-names = "axi", "ahb", "smmu_axi";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pcie0: qcom,pcie@00600000 {
+ compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
+ status = "disabled";
+ power-domains = <&gcc PCIE0_GDSC>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ msi-parent = <&msi_alias0>;
+
+ reg = <0x00600000 0x2000>,
+ <0x0c000000 0xf1d>,
+ <0x0c000f20 0xa8>,
+ <0x0c100000 0x100000>;
+ reg-names = "parf", "dbi", "elbi","config";
+
+ phys = <&pciephy_0>;
+ phy-names = "pciephy";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
+ <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
+
+ interrupts = <GIC_SPI 405 IRQ_TYPE_NONE>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
+ pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
+
+
+ vdda-supply = <&pm8994_l28>;
+
+ linux,pci-domain = <0>;
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
+
+ clock-names = "pipe",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave";
+
+ };
+
+ pcie1: qcom,pcie@00608000 {
+ compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
+ power-domains = <&gcc PCIE1_GDSC>;
+ bus-range = <0x00 0xff>;
+ msi-parent = <&msi_alias0>;
+ num-lanes = <1>;
+
+ status = "disabled";
+
+ reg = <0x00608000 0x2000>,
+ <0x0d000000 0xf1d>,
+ <0x0d000f20 0xa8>,
+ <0x0d100000 0x100000>;
+
+ reg-names = "parf", "dbi", "elbi","config";
+
+ phys = <&pciephy_1>;
+ phy-names = "pciephy";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
+ <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
+
+ interrupts = <GIC_SPI 413 IRQ_TYPE_NONE>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
+ pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
+
+
+ vdda-supply = <&pm8994_l28>;
+ linux,pci-domain = <1>;
+
+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
+ <&gcc GCC_PCIE_1_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
+
+ clock-names = "pipe",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave";
+ };
+
+ pcie2: qcom,pcie@00610000 {
+ compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
+ power-domains = <&gcc PCIE2_GDSC>;
+ bus-range = <0x00 0xff>;
+ msi-parent = <&msi_alias0>;
+ num-lanes = <1>;
+ status = "disabled";
+ reg = <0x00610000 0x2000>,
+ <0x0e000000 0xf1d>,
+ <0x0e000f20 0xa8>,
+ <0x0e100000 0x100000>;
+
+ reg-names = "parf", "dbi", "elbi","config";
+
+ phys = <&pciephy_2>;
+ phy-names = "pciephy";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
+ <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
+
+ device_type = "pci";
+
+ interrupts = <GIC_SPI 421 IRQ_TYPE_NONE>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
+ pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
+
+ vdda-supply = <&pm8994_l28>;
+
+ linux,pci-domain = <2>;
+ clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
+ <&gcc GCC_PCIE_2_AUX_CLK>,
+ <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
+
+ clock-names = "pipe",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave";
+ };
+ };
+
+ adreno_smmu: arm,smmu@b40000 {
+ compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+ reg = <0xb40000 0x10000>;
+
+ #global-interrupts = <1>;
+ interrupts = <0 334 0>,
+ <0 329 0>,
+ <0 330 0>;
+ #iommu-cells = <1>;
+
+ clocks = <&mmcc GPU_AHB_CLK>,
+ <&gcc GCC_MMSS_BIMC_GFX_CLK>;
+ clock-names = "iface", "bus";
+
+ power-domains = <&mmcc GPU_GDSC>;
+
+ status = "okay";
+ };
+
+ gpu@b00000 {
+ compatible = "qcom,adreno-530.2", "qcom,adreno";
+ #stream-id-cells = <16>;
+
+ reg = <0xb00000 0x3f000>;
+ reg-names = "kgsl_3d0_reg_memory";
+
+ interrupts = <0 300 0>;
+ interrupt-names = "kgsl_3d0_irq";
+
+ clocks = <&mmcc GPU_GX_GFX3D_CLK>,
+ <&mmcc GPU_AHB_CLK>,
+ <&mmcc GPU_GX_RBBMTIMER_CLK>,
+ <&gcc GCC_BIMC_GFX_CLK>,
+ <&gcc GCC_MMSS_BIMC_GFX_CLK>;
+
+ clock-names = "core",
+ "iface",
+ "rbbmtimer",
+ "mem",
+ "mem_iface";
+
+ power-domains = <&mmcc GPU_GDSC>;
+ iommus = <&adreno_smmu 0>;
+
+ qcom,gpu-quirk-two-pass-use-wfi;
+ qcom,gpu-quirk-fault-detect-mask;
+
+ /* This is a safe speed for bring up in all bin levels.
+ * This isn't the fastest the chip can go, but we can
+ * get there eventually */
+ qcom,gpu-pwrlevels {
+ compatible = "qcom,gpu-pwrlevels";
+ qcom,gpu-pwrlevel@0 {
+ qcom,gpu-freq = <510000000>;
+ };
+ qcom,gpu-pwrlevel@1 {
+ qcom,gpu-freq = <27000000>;
+ };
+ };
+
+ zap-shader {
+ memory-region = <&zap_shader_region>;
+ };
+ };
+
+ mdp_smmu: arm,smmu@d00000 {
+ compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+ reg = <0xd00000 0x10000>;
+
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+
+ power-domains = <&mmcc MDSS_GDSC>;
+
+ clocks = <&mmcc SMMU_MDP_AHB_CLK>,
+ <&mmcc SMMU_MDP_AXI_CLK>;
+ clock-names = "iface", "bus";
+
+ status = "okay";
+ };
+
+ mdss: mdss@900000 {
+ compatible = "qcom,mdss";
+
+ reg = <0x900000 0x1000>,
+ <0x9b0000 0x1040>,
+ <0x9b8000 0x1040>;
+ reg-names = "mdss_phys",
+ "vbif_phys",
+ "vbif_nrt_phys";
+
+ power-domains = <&mmcc MDSS_GDSC>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ clocks = <&mmcc MDSS_AHB_CLK>;
+ clock-names = "iface_clk";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mdp: mdp@901000 {
+ compatible = "qcom,mdp5";
+ reg = <0x901000 0x90000>;
+ reg-names = "mdp_phys";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MDSS_MDP_CLK>,
+ <&mmcc SMMU_MDP_AXI_CLK>,
+ <&mmcc MDSS_VSYNC_CLK>;
+ clock-names = "iface_clk",
+ "bus_clk",
+ "core_clk",
+ "iommu_clk",
+ "vsync_clk";
+
+ iommus = <&mdp_smmu 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdp5_intf3_out: endpoint {
+ remote-endpoint = <&hdmi_in>;
+ };
+ };
+ };
+ };
+
+ hdmi: hdmi-tx@9a0000 {
+ compatible = "qcom,hdmi-tx-8996";
+ reg = <0x009a0000 0x50c>,
+ <0x00070000 0x6158>,
+ <0x009e0000 0xfff>;
+ reg-names = "core_physical",
+ "qfprom_physical",
+ "hdcp_physical";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_HDMI_CLK>,
+ <&mmcc MDSS_HDMI_AHB_CLK>,
+ <&mmcc MDSS_EXTPCLK_CLK>;
+ clock-names =
+ "mdp_core_clk",
+ "iface_clk",
+ "core_clk",
+ "alt_iface_clk",
+ "extp_clk";
+
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi_phy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ hdmi_in: endpoint {
+ remote-endpoint = <&mdp5_intf3_out>;
+ };
+ };
+ };
+ };
+
+ hdmi_phy: hdmi-phy@9a0600 {
+ compatible = "qcom,hdmi-phy-8996";
+ reg = <0x9a0600 0x1c4>,
+ <0x9a0a00 0x124>,
+ <0x9a0c00 0x124>,
+ <0x9a0e00 0x124>,
+ <0x9a1000 0x124>,
+ <0x9a1200 0x0c8>;
+ reg-names = "hdmi_pll",
+ "hdmi_tx_l0",
+ "hdmi_tx_l1",
+ "hdmi_tx_l2",
+ "hdmi_tx_l3",
+ "hdmi_phy";
+
+ clocks = <&mmcc MDSS_AHB_CLK>,
+ <&gcc GCC_HDMI_CLKREF_CLK>;
+ clock-names = "iface_clk",
+ "ref_clk";
+ };
+ };
+
+ lpass_q6_smmu: arm,smmu-lpass_q6@1600000 {
+ compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+ reg = <0x1600000 0x20000>;
+ #iommu-cells = <1>;
+ power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
+
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
+ <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
+ clock-names = "iface", "bus";
+ status = "okay";
+ };
+
+ venus_smmu: arm,smmu-venus@d40000 {
+ compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+ reg = <0xd40000 0x20000>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
+ clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
+ <&mmcc SMMU_VIDEO_AXI_CLK>;
+ clock-names = "iface", "bus";
+ #iommu-cells = <1>;
+ status = "okay";
+ };
+
+ venus: video-codec@c00000 {
+ compatible = "qcom,msm8996-venus";
+ reg = <0x00c00000 0xff000>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&mmcc VENUS_GDSC>;
+ clocks = <&mmcc VIDEO_CORE_CLK>,
+ <&mmcc VIDEO_AHB_CLK>,
+ <&mmcc VIDEO_AXI_CLK>,
+ <&mmcc VIDEO_MAXI_CLK>;
+ clock-names = "core", "iface", "bus", "mbus";
+ iommus = <&venus_smmu 0x00>,
+ <&venus_smmu 0x01>,
+ <&venus_smmu 0x0a>,
+ <&venus_smmu 0x07>,
+ <&venus_smmu 0x0e>,
+ <&venus_smmu 0x0f>,
+ <&venus_smmu 0x08>,
+ <&venus_smmu 0x09>,
+ <&venus_smmu 0x0b>,
+ <&venus_smmu 0x0c>,
+ <&venus_smmu 0x0d>,
+ <&venus_smmu 0x10>,
+ <&venus_smmu 0x11>,
+ <&venus_smmu 0x21>,
+ <&venus_smmu 0x28>,
+ <&venus_smmu 0x29>,
+ <&venus_smmu 0x2b>,
+ <&venus_smmu 0x2c>,
+ <&venus_smmu 0x2d>,
+ <&venus_smmu 0x31>;
+ memory-region = <&venus_region>;
+ status = "okay";
+
+ video-decoder {
+ compatible = "venus-decoder";
+ clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
+ clock-names = "core";
+ power-domains = <&mmcc VENUS_CORE0_GDSC>;
+ };
+
+ video-encoder {
+ compatible = "venus-encoder";
+ clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
+ clock-names = "core";
+ power-domains = <&mmcc VENUS_CORE1_GDSC>;
+ };
+ };
+
+ remoteproc@2080000 {
+ compatible = "qcom,msm8996-mss-pil";
+
+ reg = <0x2080000 0x100>,
+ <0x2180000 0x040>;
+ reg-names = "qdsp6", "rmb";
+
+ interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready",
+ "handover", "stop-ack";
+
+ clocks = <&xo_board>,
+ <&gcc GCC_MSS_CFG_AHB_CLK>,
+ <&rpmcc RPM_SMD_PCNOC_CLK>,
+ <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
+ <&gcc GCC_BOOT_ROM_AHB_CLK>,
+ <&gcc GCC_MSS_GPLL0_DIV_CLK>,
+ <&gcc GCC_MSS_SNOC_AXI_CLK>,
+ <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
+ <&rpmcc RPM_SMD_QDSS_CLK>;
+
+ clock-names = "xo", "iface", "pnoc", "bus",
+ "mem", "gpll0_mss_clk", "snoc_axi_clk",
+ "mnoc_axi_clk", "qdss";
+
+ mx-supply = <&pm8994_s2>;
+ cx-supply = <&pm8994_s1>;
+ pll-supply = <&pm8994_l12>;
+
+ resets = <&gcc GCC_MSS_RESTART>;
+ reset-names = "mss_restart";
+
+ qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
+
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ mba {
+ memory-region = <&mba_region>;
+ };
+
+ mpss {
+ memory-region = <&mpss_region>;
+ };
+
+ smd-edge {
+ interrupts = <0 449 IRQ_TYPE_EDGE_RISING>;
+
+ label = "modem";
+ mboxes = <&apcs_glb 12>;
+ qcom,smd-edge = <0>;
+ qcom,remote-pid = <1>;
+ };
+ };
+ };
+
+ sound: sound {
+
};
adsp-pil {
@@ -847,6 +1942,51 @@
qcom,ipc = <&apcs 16 8>;
qcom,smd-edge = <1>;
qcom,remote-pid = <2>;
+
+ apr {
+ compatible = "qcom,apr-v2";
+ qcom,smd-channels = "apr_audio_svc";
+ qcom,apr-dest-domain-id = <APR_DOMAIN_ADSP>;
+
+ q6core {
+ qcom,apr-svc-name = "CORE";
+ qcom,apr-svc-id = <APR_SVC_ADSP_CORE>;
+ compatible = "qcom,q6core";
+ };
+
+ q6afe: q6afe {
+ compatible = "qcom,q6afe";
+ qcom,apr-svc-name = "AFE";
+ qcom,apr-svc-id = <APR_SVC_AFE>;
+ q6afedai: dais {
+ compatible = "qcom,q6afe-dai";
+ #sound-dai-cells = <1>;
+ };
+ };
+
+ q6asm: q6asm {
+ compatible = "qcom,q6asm";
+ qcom,apr-svc-name = "ASM";
+ qcom,apr-svc-id = <APR_SVC_ASM>;
+ q6asmdai: dais {
+ compatible = "qcom,q6asm-dai";
+ #sound-dai-cells = <1>;
+ power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
+ iommus = <&lpass_q6_smmu 1>;
+ };
+ };
+
+ q6adm: q6adm {
+ compatible = "qcom,q6adm";
+ qcom,apr-svc-name = "ADM";
+ qcom,apr-svc-id = <APR_SVC_ADM>;
+ q6routing: routing {
+ compatible = "q6routing";
+ #sound-dai-cells = <0>;
+ };
+ };
+
+ };
};
};
@@ -923,3 +2063,5 @@
};
#include "msm8996-pins.dtsi"
+#include "pm8994.dtsi"
+#include "pmi8994.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi
index 0223e60d8b6a..92d70def5705 100644
--- a/arch/arm64/boot/dts/qcom/pm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi
@@ -97,6 +97,14 @@
#address-cells = <1>;
#size-cells = <0>;
+ pm8916_pwm: pwm@bc00 {
+ compatible = "qcom,pm8916-pwm";
+
+ #pwm-cells = <2>;
+
+ status = "disabled";
+ };
+
wcd_codec: codec@f000 {
compatible = "qcom,pm8916-wcd-analog-codec";
reg = <0xf000 0x200>;
@@ -139,5 +147,123 @@
};
+ regulators {
+ compatible = "qcom,pm8916-regulators";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ s1@1400 {
+ reg = <0x1400 0x300>;
+ status = "disabled";
+ };
+
+ pm8916_spmi_s2: s2@1700 {
+ reg = <0x1700 0x300>;
+ status = "ok";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ };
+
+ s3@1a00 {
+ reg = <0x1a00 0x300>;
+ status = "disabled";
+ };
+
+ s4@1d00 {
+ reg = <0x1d00 0x300>;
+ status = "disabled";
+ };
+
+ l1@4000 {
+ reg = <0x4000 0x100>;
+ status = "disabled";
+ };
+
+ l2@4100 {
+ reg = <0x4100 0x100>;
+ status = "disabled";
+ };
+
+ l3@4200 {
+ reg = <0x4200 0x100>;
+ status = "disabled";
+ };
+
+ l4@4300 {
+ reg = <0x4300 0x100>;
+ status = "disabled";
+ };
+
+ l5@4400 {
+ reg = <0x4400 0x100>;
+ status = "disabled";
+ };
+
+ l6@4500 {
+ reg = <0x4500 0x100>;
+ status = "disabled";
+ };
+
+ l7@4600 {
+ reg = <0x4600 0x100>;
+ status = "disabled";
+ };
+
+ l8@4700 {
+ reg = <0x4700 0x100>;
+ status = "disabled";
+ };
+
+ l9@4800 {
+ reg = <0x4800 0x100>;
+ status = "disabled";
+ };
+
+ l10@4900 {
+ reg = <0x4900 0x100>;
+ status = "disabled";
+ };
+
+ l11@4a00 {
+ reg = <0x4a00 0x100>;
+ status = "disabled";
+ };
+
+ l12@4b00 {
+ reg = <0x4b00 0x100>;
+ status = "disabled";
+ };
+
+ l13@4c00 {
+ reg = <0x4c00 0x100>;
+ status = "disabled";
+ };
+
+ l14@4d00 {
+ reg = <0x4d00 0x100>;
+ status = "disabled";
+ };
+
+ l15@4e00 {
+ reg = <0x4e00 0x100>;
+ status = "disabled";
+ };
+
+ l16@4f00 {
+ reg = <0x4f00 0x100>;
+ status = "disabled";
+ };
+
+ l17@5000 {
+ reg = <0x5000 0x100>;
+ status = "disabled";
+ };
+
+ l18@5100 {
+ reg = <0x5100 0x100>;
+ status = "disabled";
+ };
+ };
};
};
diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi
index 80024c0b1c7c..e90aa69c33ab 100644
--- a/arch/arm64/boot/dts/qcom/pm8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi
@@ -67,5 +67,11 @@
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
+
+ lpg {
+ compatible = "qcom,pm8994-lpg";
+
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi
index dae1cdc23f54..ecafad2c69c5 100644
--- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi
@@ -26,6 +26,17 @@
<2 0xc8 0 IRQ_TYPE_NONE>,
<2 0xc9 0 IRQ_TYPE_NONE>;
};
+
+ pmi8994_mpps: mpps@a000 {
+ compatible = "qcom,pm8994-mpp";
+ reg = <0xa000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <0 0xa0 0 IRQ_TYPE_NONE>,
+ <0 0xa1 0 IRQ_TYPE_NONE>,
+ <0 0xa2 0 IRQ_TYPE_NONE>,
+ <0 0xa3 0 IRQ_TYPE_NONE>;
+ };
};
pmic@3 {
@@ -33,5 +44,25 @@
reg = <0x3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
+
+ lpg@b100 {
+ compatible = "qcom,pmi8994-lpg";
+
+ status = "disabled";
+ };
+
+ regulators {
+ compatible = "qcom,pmi8994-regulators";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pmi8994_s2: s2@1700 {
+ reg = <0x1700 0x100>;
+ status = "ok";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1015000>;
+ regulator-always-on;
+ };
+ };
};
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-13 23:37:23 +0000