arm: dts: sdm845: Enable cameraqcomlt-5.4-sdm845-camera

Copied from robert's tree.

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>

2 files changed, 266 insertions, 64 deletions

diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
index 961ba753a11c2..86387fb8b026c 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
@@ -123,6 +123,52 @@
 		// enable-active-high;
 	};
 
+	cam0_dvdd_1v2: reg_cam0_dvdd_1v2 {
+		compatible = "regulator-fixed";
+		regulator-name = "CAM0_DVDD_1V2";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		enable-active-high;
+		gpio = <&pm8998_gpio 12 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cam0_dvdd_1v2_en_default>;
+		vin-supply = <&vbat>;
+	};
+
+	cam0_avdd_2v8: reg_cam0_avdd_2v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "CAM0_AVDD_2V8";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+		enable-active-high;
+		gpio = <&pm8998_gpio 10 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cam0_avdd_2v8_en_default>;
+		vin-supply = <&vbat>;
+	};
+
+	/* This regulator is enabled when the VREG_LVS1A_1P8 trace is enabled */
+	cam3_avdd_2v8: reg_cam3_avdd_2v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "CAM3_AVDD_2V8";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+		regulator-always-on;
+		vin-supply = <&vbat>;
+	};
+
+	/* This regulator does not really exits, but a 'vddd-supply' is required
+	 * for the ov7251 driver, but no 'vddd' regulator is used in the schematic
+	 */
+	cam3_vddd_1v2: reg_cam3_vddd_1v2 {
+		compatible = "regulator-fixed";
+		regulator-name = "CAM3_VDDD_1V2_DUMMY";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-always-on;
+		vin-supply = <&vbat>;
+	};
+
 	pcie0_3p3v_dual: vldo-3v3-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "VLDO_3V3";
@@ -703,6 +749,50 @@
 };
 
 &tlmm {
+	cam0_default: cam0_default {
+		mux_rst {
+			function = "gpio";
+			pins = "gpio9";
+		};
+		config_rst {
+			pins = "gpio9";
+			drive-strength = <16>;
+			bias-disable;
+		};
+
+		mux_mclk0 {
+			function = "cam_mclk";
+			pins = "gpio13";
+		};
+		config_mclk0 {
+			pins = "gpio13";
+			drive-strength = <16>;
+			bias-disable;
+		};
+	};
+
+	cam3_default: cam3_default {
+			mux_rst {
+				function = "gpio";
+				pins = "gpio21";
+			};
+			config_rst {
+				pins = "gpio21";
+				drive-strength = <16>;
+				bias-disable;
+			};
+
+			mux_mclk3 {
+				function = "cam_mclk";
+				pins = "gpio16";
+			};
+			config_mclk3 {
+				pins = "gpio16";
+				drive-strength = <16>;
+				bias-disable;
+			};
+	};
+
 	pcie0_default_state: pcie0-default {
 		clkreq {
 			pins = "gpio36";
@@ -1006,8 +1096,122 @@
 		"PM845_GPIO24",
 		"OPTION2",
 		"PM845_SLB";
+
+	cam0_dvdd_1v2_en_default: cam0_dvdd_1v2_en_pinctrl {
+		pins = "gpio12";
+		function = "normal";
+
+		bias-pull-up;
+		drive-push-pull;
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+	};
+
+	cam0_avdd_2v8_en_default: cam0_avdd_2v8_en_pinctrl {
+		pins = "gpio10";
+		function = "normal";
+
+		bias-pull-up;
+		drive-push-pull;
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
+	};
 };
 
 &cci {
 	status = "ok";
+
+	i2c-bus@0 {
+		cam0@20 {
+			compatible = "ovti,ov8856";
+
+			// I2C address as per db845c mezzanine schematic
+			reg = <0x20>;
+
+			// CAM0_RST_N
+			reset-gpios = <&tlmm 9 GPIO_ACTIVE_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&cam0_default>;
+			gpios = <&tlmm 13 0>,
+				<&tlmm 9 0>;
+
+			clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+			clock-names = "xvclk";
+			clock-frequency = <19200000>;
+
+
+			/* The &vreg_s4a_1p8 trace is powered on as a
+			 * part of the TITAN_TOP_GDSC power domain.
+			 * So it is represented by a fixed regulator.
+			 *
+			 * The 2.8V vdda-supply and 1.2V vddd-supply regulators
+			 * both have to be enabled through the power management
+			 * gpios.
+			 */
+			power-domains = <&clock_camcc TITAN_TOP_GDSC>;
+
+			dovdd-supply = <&vreg_lvs1a_1p8>;
+			avdd-supply = <&cam0_avdd_2v8>;
+			dvdd-supply = <&cam0_dvdd_1v2>;
+
+			/* No camera mezzanine by default */
+			status = "okay";
+
+			port {
+				ov8856_ep: endpoint {
+					clock-lanes = <1>;
+					link-frequencies = /bits/ 64
+						<360000000 180000000>;
+					data-lanes = <1 2 3 4>;
+//					remote-endpoint = <&csiphy0_ep>;
+				};
+			};
+		};
+	};
+
+	i2c-bus@1 {
+		cam3@60 {
+			compatible = "ovti,ov7251";
+
+			// I2C address as per ov7251.txt linux documentation
+			reg = <0x60>;
+
+			// CAM3_RST_N
+			enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&cam3_default>;
+			gpios = <&tlmm 16 0>,
+				<&tlmm 21 0>;
+
+			clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+			clock-names = "xclk";
+			clock-frequency = <24000000>;
+
+			/* The &vreg_s4a_1p8 trace is powered on as a
+			 * part of the TITAN_TOP_GDSC power domain.
+			 * So it is represented by a fixed regulator.
+			 *
+			 * The 2.8V vdda-supply regulator is enabled when the
+			 * vreg_s4a_1p8 trace is pulled high.
+			 * It too is represented by a fixed regulator.
+			 *
+			 * No 1.2V vddd-supply regulator is used, a fixed
+			 * regulator represents it.
+			 */
+			power-domains = <&clock_camcc TITAN_TOP_GDSC>;
+
+			vdddo-supply = <&vreg_lvs1a_1p8>;
+			vdda-supply = <&cam3_avdd_2v8>;
+			vddd-supply = <&cam3_vddd_1v2>;
+
+			/* No camera mezzanine by default */
+			status = "okay";
+
+			port {
+				ov7251_ep: endpoint {
+					clock-lanes = <1>;
+					data-lanes = <0 1>;
+//					remote-endpoint = <&csiphy3_ep>;
+				};
+			};
+		};
+	};
 };
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index ea78ecb1e568b..7c1869159f892 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -765,6 +765,51 @@
 		dma-ranges = <0 0 0 0 0x10 0>;
 		compatible = "simple-bus";
 
+		cci: cci@ac4a000 {
+			compatible = "qcom,sdm845-cci";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			reg = <0 0xac4a000 0 0x4000>;
+			interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
+			power-domains = <&clock_camcc TITAN_TOP_GDSC>;
+
+			clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
+				<&clock_camcc CAM_CC_SOC_AHB_CLK>,
+				<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+				<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
+				<&clock_camcc CAM_CC_CCI_CLK>,
+				<&clock_camcc CAM_CC_CCI_CLK_SRC>;
+			clock-names = "camnoc_axi_clk",
+				"soc_ahb_clk",
+				"slow_ahb_src_clk",
+				"cpas_ahb_clk",
+				"cci",
+				"cci_clk_src";
+
+			assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
+				<&clock_camcc CAM_CC_CCI_CLK>;
+			assigned-clock-rates = <80000000>, <37500000>;
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&cci0_default &cci1_default>;
+			pinctrl-1 = <&cci0_suspend &cci1_suspend>;
+
+			status = "ok";
+
+			i2c-bus@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			i2c-bus@1 {
+				reg = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
 		gcc: clock-controller@100000 {
 			compatible = "qcom,gcc-sdm845";
 			reg = <0 0x00100000 0 0x1f0000>;
@@ -1735,8 +1780,8 @@
 				};
 				pinconf {
 					pins = "gpio17", "gpio18";
-					drive-strength = <16>;
-					bias-disable;
+					bias-pull-up; /* PULL UP*/
+					drive-strength = <2>; /* 2 MA */
 				};
 			};
 
@@ -1762,8 +1807,8 @@
 				};
 				pinconf {
 					pins = "gpio19", "gpio20";
-					drive-strength = <16>;
-					bias-disable;
+					bias-pull-up; /* PULL UP*/
+					drive-strength = <2>; /* 2 MA */
 				};
 			};
 
@@ -2925,19 +2970,19 @@
 				reg = <1>;
 				#address-cells = <1>;
 				#size-cells = <1>;
-	
+
 				wcd9340_ifd: tas-ifd {
 					compatible = "slim217,250";
 					reg  = <0 0>;
 				};
-	
+
 				wcd9340: codec@1{
 					pinctrl-0 = <&wcd_intr_default>;
 					pinctrl-names = "default";
 					compatible = "slim217,250";
 					reg  = <1 0>;
 					reset-gpios = <&tlmm 64 0>;
-					slim-ifc-dev  = <&wcd9340_ifd>;	
+					slim-ifc-dev  = <&wcd9340_ifd>;
 
 					#sound-dai-cells = <1>;
 
@@ -2953,7 +2998,7 @@
 					qcom,micbias2-millivolt = <1800>;
 					qcom,micbias3-millivolt = <1800>;
 					qcom,micbias4-millivolt = <1800>;
-				
+
 					#address-cells = <1>;
 					#size-cells = <1>;
 
@@ -2967,51 +3012,51 @@
 							mux {
 								pins = "gpio1";
 							};
-			
+
 							config {
 								pins = "gpio1";
 								output-high;
 							};
 						};
-			
+
 						spkr_1_wcd_en_sleep: spkr_1_wcd_en_sleep {
 							mux {
 								pins = "gpio1";
 							};
-			
+
 							config {
 								pins = "gpio1";
 								input-enable;
 							};
 						};
-			
+
 						spkr_2_wcd_en_active: spkr_2_sd_n_active {
 							mux {
 								pins = "gpio2";
 							};
-			
+
 							config {
 								pins = "gpio2";
 								output-high;
 							};
 						};
-			
+
 						spkr_2_wcd_en_sleep: spkr_2_sd_n_sleep {
 							mux {
 								pins = "gpio2";
 							};
-			
+
 							config {
 								pins = "gpio2";
 								input-enable;
 							};
 						};
-			
+
 						hph_en0_wcd_active: hph_en0_wcd_active {
 							mux {
 								pins = "gpio4";
 							};
-			
+
 							config {
 								pins = "gpio4";
 								output-high;
@@ -3267,53 +3312,6 @@
 			#reset-cells = <1>;
 		};
 
-		cci: cci@ac4a000 {
-			compatible = "qcom,sdm845-cci";
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			reg = <0 0xac4a000 0 0x4000>;
-			interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
-			power-domains = <&clock_camcc TITAN_TOP_GDSC>;
-
-			clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
-				<&clock_camcc CAM_CC_SOC_AHB_CLK>,
-				<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
-				<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
-				<&clock_camcc CAM_CC_CCI_CLK>,
-				<&clock_camcc CAM_CC_CCI_CLK_SRC>;
-			clock-names = "camnoc_axi_clk",
-				"soc_ahb_clk",
-				"slow_ahb_src_clk",
-				"cpas_ahb_clk",
-				"cci",
-				"cci_clk_src";
-
-			assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
-				<&clock_camcc CAM_CC_CCI_CLK>;
-			assigned-clock-rates = <80000000>, <37500000>;
-
-			pinctrl-names = "default, suspend";
-			pinctrl-0 = <&cci0_default &cci1_default>;
-			pinctrl-1 = <&cci0_suspend &cci1_suspend>;
-
-			status = "disabled";
-
-			i2c-bus@0 {
-				reg = <0>;
-				clock-frequency = <1000000>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-			};
-
-			i2c-bus@1 {
-				reg = <1>;
-				clock-frequency = <1000000>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-			};
-		};
-
 		mdss: mdss@ae00000 {
 			compatible = "qcom,sdm845-mdss";
 			reg = <0 0x0ae00000 0 0x1000>;