diff options
| author | Loic Poulain <loic.poulain@linaro.org> | 2020-05-14 09:30:39 +0200 |
|---|---|---|
| committer | Loic Poulain <loic.poulain@linaro.org> | 2020-05-14 09:30:39 +0200 |
| commit | 987d898b8e6ac44e7aca4dcb5631d9c65aa3867b (patch) | |
| tree | c3abc1b00f137bc90b47b1d21412b67a47fe6cac | |
| parent | d482e067fe6eebcdb4f870cd668133c20be6bf2a (diff) | |
fix ongoing from lkmldb820c-fixes
| -rw-r--r-- | drivers/clk/qcom/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/clk/qcom/clk-cpu-8996.c | 20 |
2 files changed, 9 insertions, 13 deletions
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 41fd197a93f34..d00cd367bb3af 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -39,8 +39,6 @@ config QCOM_CLK_APCS_MSM8916 config QCOM_CLK_APCC_MSM8996 tristate "MSM8996 CPU Clock Controller" - depends on ARM64 - depends on COMMON_CLK_QCOM select QCOM_KRYO_L2_ACCESSORS help Support for the CPU clock controller on msm8996 devices. diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index a977d5a82fa9a..75ae6ac6ef52f 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -32,9 +32,7 @@ * * The primary PLL is what drives the CPU clk, except for times * when we are reprogramming the PLL itself (for rate changes) when - * we temporarily switch to an alternate PLL. A subsequent patch adds - * support to switch between primary and alternate PLL during rate - * changes. + * we temporarily switch to an alternate PLL. * * The primary PLL operates on a single VCO range, between 600MHz * and 3GHz. However the CPUs do support OPPs with frequencies @@ -427,7 +425,7 @@ static int qcom_cpu_clk_msm8996_unregister_clks(void) #define L2ACDDVMRC_REG 0x584ULL #define L2ACDSSCR_REG 0x589ULL -static DEFINE_SPINLOCK(acd_lock); +static DEFINE_SPINLOCK(qcom_clk_acd_lock); static void __iomem *base; static void qcom_cpu_clk_msm8996_acd_init(void __iomem *base) @@ -435,27 +433,27 @@ static void qcom_cpu_clk_msm8996_acd_init(void __iomem *base) u64 hwid; unsigned long flags; - spin_lock_irqsave(&acd_lock, flags); + spin_lock_irqsave(&qcom_clk_acd_lock, flags); hwid = read_cpuid_mpidr() & CPU_AFINITY_MASK; kryo_l2_set_indirect_reg(L2ACDTD_REG, 0x00006A11); - kryo_l2_set_indirect_reg(L2ACDDVMRC_REG, 0x000E0F0F); + kryo_l2_set_indirect_reg(L2ACDDVMRC_REG, 0x000e0f0f); kryo_l2_set_indirect_reg(L2ACDSSCR_REG, 0x00000601); if (PWRCL_CPU_REG_MASK == (hwid | PWRCL_CPU_REG_MASK)) { - writel(0xF, base + PWRCL_REG_OFFSET + SSSCTL_OFFSET); + writel(0xf, base + PWRCL_REG_OFFSET + SSSCTL_OFFSET); wmb(); - kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002C5FFD); + kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002c5ffd); } if (PERFCL_CPU_REG_MASK == (hwid | PERFCL_CPU_REG_MASK)) { - kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002C5FFD); - writel(0xF, base + PERFCL_REG_OFFSET + SSSCTL_OFFSET); + kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002c5ffd); + writel(0xf, base + PERFCL_REG_OFFSET + SSSCTL_OFFSET); wmb(); } - spin_unlock_irqrestore(&acd_lock, flags); + spin_unlock_irqrestore(&qcom_clk_acd_lock, flags); } static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, |