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tag namepinctrl-v4.15-2 (1cb5f161db49f10045644b7c91761d095429717a)
tag date2017-12-05 14:11:14 +0100
tagged byLinus Walleij <linus.walleij@linaro.org>
tagged objectcommit 07c43a382d...
Pin control fixes for the v4.15 cycle:
- Fix the UART2 RTS pin mode on Intel Denverton. - Fix the direction_output() behaviour on the Armada 37xx. - Fix the groups selection per-SoC on the Gemini. - Fix the interrupt pin bank on the Sunxi A80. - Fix the UART mux on the Sunxi A64. - Disable the strict mode on the Sunxi H5 driver. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJaJpuUAAoJEEEQszewGV1zaEwQAJhvSs4drBr8UNNH1Kg9FS7p yyrxHKYpgqzjvAxokZuffw/FBqLZfufih+o0SIk9icsllmDfN4GFTL4E5mVKETgH 9/4R5So8mMDiSEjzWqKG+NwREgMx6Xz5JR68GTIgEmIn5HYDuv3WT3yhfLQrNt2B 0CaWe3raRZ7zagj2DRx8E5NPL6pXiMFGsz0PPTmuOpc6Nfo47KOo7xgxUmTRUA8N SsjM6DwkAzMPv1Z99izWsadcKP1qFzVf+5mOdna/rDfffm+33T3+Cw5R3KEtl512 4Kyx4URGcQY/fCvYm4pIxOkS2/iGi3/MaDYcSR0MaogGJ7IOFBiSD0xZ3Opp90Bn +M/oTdH1CiHjOYUCyFW9P44aTE2bG2LEELW7am4cjyTTRE/ioy2ARC8/2v4QaLZ5 U3r/tjs+gIDb+nwUuxLbibT1V9j4JZ2QCp9o9k7VCmsXVsKYwTgbIR4AfpvBzUCd Y+C9aBux5ns7NTNv7xnhbBWn8lH+9pT7BHmNQI7Ru7eRkosWoz3pZ+BijvV+exeQ 7dCec7rj+lDyDmnvjxwcdhsXv+l/JIap5fK3RHWLxpjJ/Ct5EsnMII6eh2InPC4E 2GvusJBOb5etUms25V/tVUY+v2vIF8UDUg9qkZSDBX7+zuKNng4h3XotB81rR70K 0uxFl7X2hW1midI7hJCC =/auO -----END PGP SIGNATURE-----