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authorVoon Weifeng <weifeng.voon@intel.com>2021-06-08 11:51:56 +0800
committerDavid S. Miller <davem@davemloft.net>2021-06-08 14:31:43 -0700
commit597a68ce32167e7d07bf40648e1501f786f60f99 (patch)
treef954de48a3e1b9de82024aae9f1da6aed627f99c /drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
parent303597e49b835471dc571849af02a99fa74ba3ae (diff)
downloadandroid-dev-597a68ce32167e7d07bf40648e1501f786f60f99.tar.gz
net: stmmac: split xPCS setup from mdio register
This patch is a preparation patch for the enabling of Intel mGbE 2.5Gbps link speed. The Intel mGbR link speed configuration (1G/2.5G) is depends on a mdio ADHOC register which can be configured in the bios menu. As PHY interface might be different for 1G and 2.5G, the mdio bus need be ready to check the link speed and select the PHY interface before probing the xPCS. Signed-off-by: Voon Weifeng <weifeng.voon@intel.com> Signed-off-by: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/stmicro/stmmac/stmmac_main.c')
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/stmmac_main.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 0a266fa0af7e..af406ea3dd46 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -6993,6 +6993,14 @@ int stmmac_dvr_probe(struct device *device,
}
}
+ if (priv->plat->mdio_bus_data) {
+ if (priv->plat->mdio_bus_data->has_xpcs) {
+ ret = stmmac_xpcs_setup(priv->mii);
+ if (ret)
+ goto error_xpcs_setup;
+ }
+ }
+
ret = stmmac_phy_setup(priv);
if (ret) {
netdev_err(ndev, "failed to setup phy (%d)\n", ret);
@@ -7029,6 +7037,7 @@ error_serdes_powerup:
unregister_netdev(ndev);
error_netdev_register:
phylink_destroy(priv->phylink);
+error_xpcs_setup:
error_phy_setup:
if (priv->hw->pcs != STMMAC_PCS_TBI &&
priv->hw->pcs != STMMAC_PCS_RTBI)