1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
|
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include "ddp_clkmgr.h"
#include <ddp_pwm_mux.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "ddp_reg.h"
#define PWM_MSG(fmt, arg...) pr_debug("[PWM] " fmt "\n", ##arg)
#define PWM_ERR(fmt, arg...) pr_err("[PWM] " fmt "\n", ##arg)
/*****************************************************************************
*
* variable for get clock node fromdts
*
*****************************************************************************/
static void __iomem *disp_pmw_mux_base;
#ifndef MUX_DISPPWM_ADDR /* disp pwm source clock select register address */
#define MUX_DISPPWM_ADDR (disp_pmw_mux_base + 0x50)
#endif
#ifdef HARD_CODE_CONFIG
#ifndef MUX_UPDATE_ADDR /* disp pwm source clock update register address */
#define MUX_UPDATE_ADDR (disp_pmw_mux_base + 0x4)
#endif
#endif
#ifndef OSC_ULPOSC_ADDR /* rosc control register address */
#define OSC_ULPOSC_ADDR (disp_pmw_osc_base + 0x458)
#endif
/* clock hard code access API */
#define DRV_Reg32(addr) INREG32(addr)
#define clk_readl(addr) DRV_Reg32(addr)
#define clk_writel(addr, val) mt_reg_sync_writel(val, addr)
/*****************************************************************************
*
* disp pwm source clock select mux api
*
*****************************************************************************/
eDDP_CLK_ID disp_pwm_get_clkid(unsigned int clk_req)
{
eDDP_CLK_ID clkid = -1;
switch (clk_req) {
case 0:
clkid = ULPOSC_D8; /* ULPOSC 29M */
break;
case 1:
clkid = ULPOSC_D2; /* ULPOSC 117M */
break;
case 2:
clkid = UNIVPLL2_D4; /* PLL 104M */
break;
case 3:
clkid = ULPOSC_D3; /* ULPOSC 78M */
break;
case 4:
clkid = -1; /* Bypass config:default 26M */
break;
case 5:
clkid = ULPOSC_D10; /* ULPOSC 23M */
break;
case 6:
clkid = ULPOSC_D4; /* ULPOSC 58M */
break;
default:
clkid = -1;
break;
}
return clkid;
}
/*****************************************************************************
*
* get disp pwm source mux node
*
*****************************************************************************/
#define DTSI_TOPCKGEN "mediatek,topckgen"
static int disp_pwm_get_muxbase(void)
{
int ret = 0;
struct device_node *node;
if (disp_pmw_mux_base != NULL) {
PWM_MSG("TOPCKGEN node exist");
return 0;
}
node = of_find_compatible_node(NULL, NULL, DTSI_TOPCKGEN);
if (!node) {
PWM_ERR("DISP find TOPCKGEN node failed\n");
return -1;
}
disp_pmw_mux_base = of_iomap(node, 0);
if (!disp_pmw_mux_base) {
PWM_ERR("DISP TOPCKGEN base failed\n");
return -1;
}
PWM_MSG("find TOPCKGEN node");
return ret;
}
static unsigned int disp_pwm_get_pwmmux(void)
{
unsigned int regsrc = 0;
if (MUX_DISPPWM_ADDR != NULL)
regsrc = clk_readl(MUX_DISPPWM_ADDR);
else
PWM_ERR("mux addr illegal");
return regsrc;
}
/*****************************************************************************
*
* disp pwm source clock select mux api
*
*****************************************************************************/
int disp_pwm_set_pwmmux(unsigned int clk_req)
{
unsigned int regsrc;
int ret = 0;
eDDP_CLK_ID clkid = -1;
clkid = disp_pwm_get_clkid(clk_req);
ret = disp_pwm_get_muxbase();
regsrc = disp_pwm_get_pwmmux();
PWM_MSG("clk_req=%d clkid=%d", clk_req, clkid);
if (clkid != -1) {
ddp_clk_enable(MUX_PWM);
ddp_clk_set_parent(MUX_PWM, clkid);
ddp_clk_disable(MUX_PWM);
}
PWM_MSG("PWM_MUX %x->%x", regsrc, disp_pwm_get_pwmmux());
return 0;
}
static void __iomem *disp_pmw_osc_base;
#ifndef OSC_ULPOSC_ADDR /* rosc control register address */
#define OSC_ULPOSC_ADDR (disp_pmw_osc_base + 0x458)
#endif
/*****************************************************************************
*
* get disp pwm source osc
*
*****************************************************************************/
static int get_ulposc_base(void)
{
int ret = 0;
struct device_node *node;
if (disp_pmw_osc_base != NULL) {
PWM_MSG("SLEEP node exist");
return 0;
}
node = of_find_compatible_node(NULL, NULL, "mediatek,sleep");
if (!node) {
PWM_ERR("DISP find SLEEP node failed\n");
return -1;
}
disp_pmw_osc_base = of_iomap(node, 0);
if (!disp_pmw_osc_base) {
PWM_ERR("DISP find SLEEP base failed\n");
return -1;
}
return ret;
}
static int get_ulposc_status(void)
{
unsigned int regosc;
int ret = -1;
if (get_ulposc_base() == -1) {
PWM_ERR("get ULPOSC status fail");
return ret;
}
regosc = clk_readl(OSC_ULPOSC_ADDR);
if ((regosc & 0x5) != 0x5) {
PWM_MSG("ULPOSC is off (%x)", regosc);
ret = 0;
} else {
PWM_MSG("ULPOSC is on (%x)", regosc);
ret = 1;
}
return ret;
}
/*****************************************************************************
*
* hardcode turn on/off ROSC api
*
*****************************************************************************/
static int ulposc_on(void)
{
unsigned int regosc;
if (get_ulposc_base() == -1)
return -1;
regosc = clk_readl(OSC_ULPOSC_ADDR);
/* PWM_MSG("ULPOSC config : 0x%08x", regosc); */
/* OSC EN = 1 */
regosc = regosc | 0x1;
clk_writel(OSC_ULPOSC_ADDR, regosc);
regosc = clk_readl(OSC_ULPOSC_ADDR);
/* PWM_MSG("ULPOSC config : 0x%08x after en", regosc); */
udelay(11);
/* OSC RST */
regosc = regosc | 0x2;
clk_writel(OSC_ULPOSC_ADDR, regosc);
regosc = clk_readl(OSC_ULPOSC_ADDR);
/* PWM_MSG("ULPOSC config : 0x%08x after rst 1", regosc); */
udelay(40);
regosc = regosc & 0xfffffffd;
clk_writel(OSC_ULPOSC_ADDR, regosc);
regosc = clk_readl(OSC_ULPOSC_ADDR);
/* PWM_MSG("ULPOSC config : 0x%08x after rst 0", regosc); */
udelay(130);
/* OSC CG_EN = 1 */
regosc = regosc | 0x4;
clk_writel(OSC_ULPOSC_ADDR, regosc);
regosc = clk_readl(OSC_ULPOSC_ADDR);
/* PWM_MSG("ULPOSC config : 0x%08x after cg_en", regosc); */
return 0;
}
static int ulposc_off(void)
{
unsigned int regosc;
if (get_ulposc_base() == -1)
return -1;
regosc = clk_readl(OSC_ULPOSC_ADDR);
/* OSC CG_EN = 0 */
regosc = regosc & (~0x4);
clk_writel(OSC_ULPOSC_ADDR, regosc);
regosc = clk_readl(OSC_ULPOSC_ADDR);
/* PWM_MSG("ULPOSC config : 0x%08x after cg_en", regosc); */
udelay(40);
/* OSC EN = 0 */
regosc = regosc & (~0x1);
clk_writel(OSC_ULPOSC_ADDR, regosc);
regosc = clk_readl(OSC_ULPOSC_ADDR);
/* PWM_MSG("ULPOSC config : 0x%08x after en", regosc); */
return 0;
}
static int ulposc_enable(eDDP_CLK_ID clkid)
{
ulposc_on();
get_ulposc_status();
return 0;
}
static int ulposc_disable(eDDP_CLK_ID clkid)
{
ulposc_off();
get_ulposc_status();
return 0;
}
/*****************************************************************************
*
* disp pwm clock source power on /power off api
*
*****************************************************************************/
int disp_pwm_clksource_enable(int clk_req)
{
int ret = 0;
eDDP_CLK_ID clkid = -1;
clkid = disp_pwm_get_clkid(clk_req);
switch (clkid) {
case ULPOSC_D2:
case ULPOSC_D4:
case ULPOSC_D8:
case ULPOSC_D10:
ulposc_enable(clkid);
break;
default:
break;
}
return ret;
}
int disp_pwm_clksource_disable(int clk_req)
{
int ret = 0;
eDDP_CLK_ID clkid = -1;
clkid = disp_pwm_get_clkid(clk_req);
switch (clkid) {
case ULPOSC_D2:
case ULPOSC_D4:
case ULPOSC_D8:
case ULPOSC_D10:
ulposc_disable(clkid);
break;
default:
break;
}
return ret;
}
|
